[llvm] [AArch64] Extend condition optimizer to support unsigned comparisons (PR #144380)

[David Green via llvm-commits]

davemgreen wrote:

Hi. Ideally we would be able to come up with a formal proof to ensure we are not missing anything. Like you said some of the cases are difficult to reach though. Something like this is what I was thinking of for  mir test, that can be more concise but we can still use for testing. Different variants can be made up.
```
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -o - %s -run-pass=aarch64-condopt | FileCheck %s

---
name:            add_add_hi_hi
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: add_add_hi_hi
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[ADDSWri:%[0-9]+]]:gpr32 = ADDSWri [[COPY]], 0, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 12, %bb.1, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[ADDSWri1:%[0-9]+]]:gpr32 = ADDSWri [[COPY]], 1, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 12, %bb.2, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET undef $lr, implicit $w0
  bb.0:
    liveins: $w0
    %0:gpr32common = COPY $w0
    %4:gpr32 = ADDSWri %0:gpr32common, 0, 0, implicit-def $nzcv
    Bcc 12, %bb.2, implicit $nzcv
    B %bb.3

  bb.2:
    liveins: $w0
    %5:gpr32 = ADDSWri %0:gpr32common, 1, 0, implicit-def $nzcv
    Bcc 12, %bb.3, implicit $nzcv
    B %bb.3

  bb.3:
    liveins: $w0
    %1:gpr32 = MOVi32imm 1
    $w0 = COPY %1
    RET undef $lr, implicit $w0
...
```

https://github.com/llvm/llvm-project/pull/144380