[llvm] [AMDGPU] Try to reuse in v_cndmask register with constant from compare. (PR #148236)
Daniil Fukalov via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 13 12:25:08 PDT 2025
https://github.com/dfukalov updated https://github.com/llvm/llvm-project/pull/148236
>From 73fe705494762c0e6bba1603da66dc32a25c9ca3 Mon Sep 17 00:00:00 2001
From: Daniil Fukalov <dfukalov at gmail.com>
Date: Fri, 11 Jul 2025 13:11:59 +0200
Subject: [PATCH 1/2] Tests pre-commit.
---
.../AMDGPU/select-cmp-shared-constant-fp.ll | 1449 +++++++++++++++++
.../AMDGPU/select-cmp-shared-constant-int.ll | 975 +++++++++++
2 files changed, 2424 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
diff --git a/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
new file mode 100644
index 0000000000000..14f04a8ca05fd
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
@@ -0,0 +1,1449 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX1010 %s
+
+; Test the CMP+SELECT optimization that folds shared constants to reduce
+; register pressure.
+
+;------------------------------------------------------------------------------
+; F32 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: fcmp oeq + select with constant in true value
+define float @fcmp_select_fold_oeq_f32_imm(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_f32_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x42487ed8
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x42487ed8
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_f32_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42487ed8, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x42487ed8, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float %arg, 0x40490FDB00000000
+ %sel = select i1 %cmp, float 0x40490FDB00000000, float %other
+ ret float %sel
+}
+
+; Should be folded: fcmp oeq + select with constant in true value (commutative)
+define float @fcmp_select_fold_oeq_imm_f32(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_imm_f32:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x42487ed8
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x42487ed8
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_imm_f32:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42487ed8, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x42487ed8, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float 0x40490FDB00000000, %arg
+ %sel = select i1 %cmp, float 0x40490FDB00000000, float %other
+ ret float %sel
+}
+
+; Should be folded: fcmp one + select with constant in false value
+define float @fcmp_select_fold_one_f32_imm(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_fold_one_f32_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x402df850
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x402df850
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_f32_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x402df850, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x402df850, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one float %arg, 0x4005BF0A00000000
+ %sel = select i1 %cmp, float %other, float 0x4005BF0A00000000
+ ret float %sel
+}
+
+; Should be folded: fcmp one + select with constant in false value (commutative)
+define float @fcmp_select_fold_one_imm_f32(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_fold_one_imm_f32:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x402df850
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x402df850
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_imm_f32:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x402df850, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x402df850, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one float 0x4005BF0A00000000, %arg
+ %sel = select i1 %cmp, float %other, float 0x4005BF0A00000000
+ ret float %sel
+}
+
+; Should NOT be folded: different constants
+define float @fcmp_select_no_fold_f32_different_const(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f32_different_const:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x42487ed8
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x46487ed8
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f32_different_const:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42487ed8, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x46487ed8, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float %arg, 0x40490FDB00000000
+ %sel = select i1 %cmp, float 0x40C90FDB00000000, float %other
+ ret float %sel
+}
+
+; Should NOT be folded: fcmp oeq with constant in other position
+define float @fcmp_select_no_fold_f32_other_pos(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f32_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x42487ed8
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x42487ed8
+; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f32_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0x42487ed8, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x42487ed8, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float %arg, 0x40490FDB00000000
+ %sel = select i1 %cmp, float %other, float 0x40490FDB00000000
+ ret float %sel
+}
+
+; Should NOT be folded: unsupported comparison type
+define float @fcmp_select_no_fold_f32_unsupported_cmp(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f32_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x42487ed8
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x42487ed8
+; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f32_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x42487ed8, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x42487ed8, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp olt float %arg, 0x40490FDB00000000
+ %sel = select i1 %cmp, float %other, float 0x40490FDB00000000
+ ret float %sel
+}
+
+; Should NOT be folded: imm can be encoded into cndmask
+define float @fcmp_select_no_fold_f32_enc_imm(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f32_enc_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, 1.0, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f32_enc_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 1.0, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float %arg, 1.0
+ %sel = select i1 %cmp, float 1.0, float %other
+ ret float %sel
+}
+
+; Should NOT be folded: imm can be encoded into cndmask
+define float @fcmp_select_no_fold_f32_enc_imm_2(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f32_enc_imm_2:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, -4.0, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, -4.0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f32_enc_imm_2:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, -4.0, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, -4.0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one float -4.0, %arg
+ %sel = select i1 %cmp, float %other, float -4.0
+ ret float %sel
+}
+
+; Should NOT be folded: fcmp oeq with zero constant
+define float @fcmp_select_no_fold_oeq_f32_zero(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_oeq_f32_zero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_oeq_f32_zero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float %arg, 0.0
+ %sel = select i1 %cmp, float 0.0, float %other
+ ret float %sel
+}
+
+; Should NOT be folded: fcmp one with negative zero constant
+define float @fcmp_select_no_fold_one_f32_negzero(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_one_f32_negzero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_brev_b32 s4, 1
+; GFX900-NEXT: v_bfrev_b32_e32 v2, 1
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_one_f32_negzero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x80000000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one float -0.0, %arg ; 0x8000000000000000
+ %sel = select i1 %cmp, float %other, float -0.0 ;0x8000000000000000
+ ret float %sel
+}
+
+; NaN values should bypass the optimization due to special IEEE 754 behavior
+; fcmp oeq with NaN always returns false, so select always chooses %other
+define float @fcmp_select_no_fold_oeq_f32_nan(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_oeq_f32_nan:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_oeq_f32_nan:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, v1
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float %arg, 0x7FF8000000000000
+ %sel = select i1 %cmp, float 0x7FF8000000000000, float %other
+ ret float %sel
+}
+
+; NaN values should bypass the optimization due to special IEEE 754 behavior
+; fcmp one with NaN always returns false, so select always chooses the NaN constant
+define float @fcmp_select_no_fold_one_f32_nan(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_one_f32_nan:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_one_f32_nan:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, 0x7fc00000
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one float 0x7FF8000000000000, %arg
+ %sel = select i1 %cmp, float %other, float 0x7FF8000000000000
+ ret float %sel
+}
+
+; Should NOT be folded: fcmp one with positive infinity
+; Infinity values should bypass the optimization, generating unfolded code
+define float @fcmp_select_no_fold_posinf_oeq_f32(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_posinf_oeq_f32:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_posinf_oeq_f32:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x7f800000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq float %arg, 0x7FF0000000000000
+ %sel = select i1 %cmp, float 0x7FF0000000000000, float %other
+ ret float %sel
+}
+
+; Should NOT be folded: fcmp one with negative infinity
+; Infinity values should bypass the optimization, generating unfolded code
+define float @fcmp_select_no_fold_neginf_f32_one(float %arg, float %other) {
+; GFX900-LABEL: fcmp_select_no_fold_neginf_f32_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xff800000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0xff800000
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_neginf_f32_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0xff800000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xff800000, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one float 0xFFF0000000000000, %arg
+ %sel = select i1 %cmp, float %other, float 0xFFF0000000000000
+ ret float %sel
+}
+
+;------------------------------------------------------------------------------
+; F64 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: f64 fcmp oeq + select with constant in true value
+define double @fcmp_select_fold_oeq_f64_imm(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_f64_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX900-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x54442d18
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x400921fb
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_f64_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX1010-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x54442d18, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x400921fb, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 3.141592653589793
+ %sel = select i1 %cmp, double 3.141592653589793, double %other
+ ret double %sel
+}
+; Should be folded: f64 fcmp oeq + select with constant in true value (commutative)
+define double @fcmp_select_fold_oeq_imm_f64(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_imm_f64:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX900-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x54442d18
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x400921fb
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_imm_f64:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX1010-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x54442d18, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x400921fb, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double 3.141592653589793, %arg
+ %sel = select i1 %cmp, double 3.141592653589793, double %other
+ ret double %sel
+}
+
+; Should be folded: f64 fcmp one + select with constant in false value
+define double @fcmp_select_fold_one_f64_imm(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_fold_one_f64_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x8b145769
+; GFX900-NEXT: s_mov_b32 s5, 0x4005bf0a
+; GFX900-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x8b145769
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x4005bf0a
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_f64_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0x8b145769
+; GFX1010-NEXT: s_mov_b32 s5, 0x4005bf0a
+; GFX1010-NEXT: v_cmp_lg_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x8b145769, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x4005bf0a, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one double %arg, 2.718281828459045
+ %sel = select i1 %cmp, double %other, double 2.718281828459045
+ ret double %sel
+}
+; Should be folded: f64 fcmp one + select with constant in false value (commutative)
+define double @fcmp_select_fold_one_imm_f64(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_fold_one_imm_f64:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x8b145769
+; GFX900-NEXT: s_mov_b32 s5, 0x4005bf0a
+; GFX900-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x8b145769
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x4005bf0a
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_imm_f64:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0x8b145769
+; GFX1010-NEXT: s_mov_b32 s5, 0x4005bf0a
+; GFX1010-NEXT: v_cmp_lg_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x8b145769, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x4005bf0a, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one double 2.718281828459045, %arg
+ %sel = select i1 %cmp, double %other, double 2.718281828459045
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with constant in other position
+define double @fcmp_select_no_fold_f64_other_pos(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f64_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX900-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX900-NEXT: v_cmp_eq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x54442d18
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x400921fb
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f64_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX1010-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX1010-NEXT: v_cmp_eq_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x54442d18, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x400921fb, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 3.141592653589793
+ %sel = select i1 %cmp, double %other, double 3.141592653589793
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp unsupported comparison type
+define double @fcmp_select_no_fold_f64_unsupported_cmp(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f64_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX900-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX900-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x54442d18
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x400921fb
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f64_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX1010-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX1010-NEXT: v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x54442d18, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x400921fb, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp olt double %arg, 3.141592653589793
+ %sel = select i1 %cmp, double %other, double 3.141592653589793
+ ret double %sel
+}
+
+; Should NOT be folded: imm can be encoded into cndmask
+define double @fcmp_select_no_fold_f64_enc_imm(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f64_enc_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, 1.0, v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x3ff00000
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f64_enc_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, 1.0, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x3ff00000, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 1.0
+ %sel = select i1 %cmp, double 1.0, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: imm can be encoded into cndmask
+define double @fcmp_select_no_fold_f64_enc_imm_2(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f64_enc_imm_2:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_lg_f64_e32 vcc, -4.0, v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v1, 0xc0100000
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f64_enc_imm_2:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f64_e32 vcc_lo, -4.0, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0xc0100000, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one double -4.0, %arg
+ %sel = select i1 %cmp, double %other, double -4.0
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with zero constant
+define double @fcmp_select_no_fold_oeq_f64_zero(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_oeq_f64_zero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, 0, v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_oeq_f64_zero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, 0, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 0.0
+ %sel = select i1 %cmp, double 0.0, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp one with negative zero constant
+define double @fcmp_select_no_fold_one_f64_negzero(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_one_f64_negzero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0
+; GFX900-NEXT: s_brev_b32 s5, 1
+; GFX900-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_bfrev_b32_e32 v1, 1
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_one_f64_negzero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0x80000000, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x80000000, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one double -0.0, %arg
+ %sel = select i1 %cmp, double %other, double -0.0
+ ret double %sel
+}
+
+; Should NOT be folded: f64 different constants
+define double @fcmp_select_no_fold_f64_different_const(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f64_different_const:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX900-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x8b145769
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x4005bf0a
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f64_different_const:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0x54442d18
+; GFX1010-NEXT: s_mov_b32 s5, 0x400921fb
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x8b145769, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x4005bf0a, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 3.141592653589793
+ %sel = select i1 %cmp, double 2.718281828459045, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with NaN constant
+; fcmp oeq with NaN always returns false, so select always chooses %other
+define double @fcmp_select_no_fold_nan_f64(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_f64:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, v3
+; GFX900-NEXT: v_mov_b32_e32 v0, v2
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_f64:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v1, v3
+; GFX1010-NEXT: v_mov_b32_e32 v0, v2
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 0x7FF8000000000000
+ %sel = select i1 %cmp, double 0x7FF8000000000000, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with NaN constant (commutative variant)
+; fcmp oeq with NaN always returns false, so select always chooses %other
+define double @fcmp_select_no_fold_nan_f64_comm(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_f64_comm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, v3
+; GFX900-NEXT: v_mov_b32_e32 v0, v2
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_f64_comm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v1, v3
+; GFX1010-NEXT: v_mov_b32_e32 v0, v2
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double 0x7FF8000000000000, %arg
+ %sel = select i1 %cmp, double 0x7FF8000000000000, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp one with NaN constant
+; fcmp one with NaN always returns false, so select always chooses the NaN constant
+define double @fcmp_select_no_fold_nan_f64_one(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_f64_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, 0
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_f64_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, 0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one double %arg, 0x7FF8000000000000
+ %sel = select i1 %cmp, double %other, double 0x7FF8000000000000
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp one with NaN constant (commutative variant)
+; fcmp one with NaN always returns false, so select always chooses the NaN constant
+define double @fcmp_select_no_fold_nan_f64_one_comm(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_f64_one_comm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, 0
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_f64_one_comm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, 0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0x7ff80000
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one double 0x7FF8000000000000, %arg
+ %sel = select i1 %cmp, double %other, double 0x7FF8000000000000
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with positive infinity
+; Infinity values should bypass the optimization, generating unfolded code
+define double @fcmp_select_no_fold_posinf_f64(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_posinf_f64:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0
+; GFX900-NEXT: s_mov_b32 s5, 0x7ff00000
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff00000
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_posinf_f64:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x7ff00000, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 0x7FF0000000000000
+ %sel = select i1 %cmp, double 0x7FF0000000000000, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with negative infinity
+; Infinity values should bypass the optimization, generating unfolded code
+define double @fcmp_select_no_fold_neginf_f64(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_neginf_f64:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0
+; GFX900-NEXT: s_mov_b32 s5, 0xfff00000
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v1, 0xfff00000
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_neginf_f64:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, 0xfff00000, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0xfff00000, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double %arg, 0xFFF0000000000000
+ %sel = select i1 %cmp, double 0xFFF0000000000000, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with positive infinity (commutative variant)
+; Infinity values should bypass the optimization, generating unfolded code
+define double @fcmp_select_no_fold_posinf_f64_comm(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_posinf_f64_comm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0
+; GFX900-NEXT: s_mov_b32 s5, 0x7ff00000
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7ff00000
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_posinf_f64_comm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x7ff00000, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double 0x7FF0000000000000, %arg
+ %sel = select i1 %cmp, double 0x7FF0000000000000, double %other
+ ret double %sel
+}
+
+; Should NOT be folded: f64 fcmp oeq with negative infinity (commutative variant)
+; Infinity values should bypass the optimization, generating unfolded code
+define double @fcmp_select_no_fold_neginf_f64_comm(double %arg, double %other) {
+; GFX900-LABEL: fcmp_select_no_fold_neginf_f64_comm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0
+; GFX900-NEXT: s_mov_b32 s5, 0xfff00000
+; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v1, 0xfff00000
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_neginf_f64_comm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, 0xfff00000, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0xfff00000, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq double 0xFFF0000000000000, %arg
+ %sel = select i1 %cmp, double 0xFFF0000000000000, double %other
+ ret double %sel
+}
+
+;------------------------------------------------------------------------------
+; F16 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: f16 fcmp oeq + select with constant in true value
+define half @fcmp_select_fold_oeq_f16_imm(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_f16_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x4248
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_neq_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_f16_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f16_e32 vcc_lo, 0x4248, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq half %arg, 0xH4248
+ %sel = select i1 %cmp, half 0xH4248, half %other
+ ret half %sel
+}
+
+; Should be folded: f16 fcmp oeq + select with constant in true value (commutative)
+define half @fcmp_select_fold_oeq_imm_f16(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_imm_f16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x4248
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_neq_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_imm_f16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f16_e32 vcc_lo, 0x4248, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq half 0xH4248, %arg
+ %sel = select i1 %cmp, half 0xH4248, half %other
+ ret half %sel
+}
+
+; Should be folded: f16 fcmp one + select with constant in false value
+define half @fcmp_select_fold_one_f16_imm(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_fold_one_f16_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x4020
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
+; GFX900-NEXT: v_cmp_lg_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_f16_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0x4020, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one half %arg, 0xH4020
+ %sel = select i1 %cmp, half %other, half 0xH4020
+ ret half %sel
+}
+
+; Should be folded: f16 fcmp one + select with constant in false value (commutative)
+define half @fcmp_select_fold_one_imm_f16(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_fold_one_imm_f16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x4020
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
+; GFX900-NEXT: v_cmp_lg_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_imm_f16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0x4020, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one half 0xH4020, %arg
+ %sel = select i1 %cmp, half %other, half 0xH4020
+ ret half %sel
+}
+
+; Should NOT be folded: different constants
+define half @fcmp_select_no_fold_f16_different_const(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f16_different_const:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x4248
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4300
+; GFX900-NEXT: v_cmp_neq_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f16_different_const:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f16_e32 vcc_lo, 0x4248, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4300, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq half %arg, 0xH4248
+ %sel = select i1 %cmp, half 0xH4300, half %other
+ ret half %sel
+}
+
+; Should NOT be folded: NaN values bypass optimization
+define half @fcmp_select_no_fold_nan_f16(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_f16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_f16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, v1
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq half %arg, 0xH7e00
+ %sel = select i1 %cmp, half 0xH7e00, half %other
+ ret half %sel
+}
+
+; Should NOT be folded: f16 fcmp one with NaN constant
+define half @fcmp_select_no_fold_nan_f16_one(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_f16_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, 0x7e00
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_f16_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, 0x7e00
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one half %arg, 0xH7e00
+ %sel = select i1 %cmp, half %other, half 0xH7e00
+ ret half %sel
+}
+
+; Should NOT be folded: f16 fcmp one with +Inf constant
+define half @fcmp_select_no_fold_posinf_f16_one(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_posinf_f16_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7c00
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7c00
+; GFX900-NEXT: v_cmp_lg_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_posinf_f16_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0x7c00, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one half %arg, 0xH7c00
+ %sel = select i1 %cmp, half %other, half 0xH7c00
+ ret half %sel
+}
+
+; Should NOT be folded: f16 fcmp one with -Inf constant
+define half @fcmp_select_no_fold_neginf_f16_one(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_neginf_f16_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xfc00
+; GFX900-NEXT: v_mov_b32_e32 v2, 0xfc00
+; GFX900-NEXT: v_cmp_lg_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_neginf_f16_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0xfc00, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xfc00, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one half %arg, 0xHfc00
+ %sel = select i1 %cmp, half %other, half 0xHfc00
+ ret half %sel
+}
+; Should NOT be folded: f16 fcmp oeq with zero constant
+define half @fcmp_select_no_fold_oeq_f16_zero(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_oeq_f16_zero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_neq_f16_e32 vcc, 0, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_oeq_f16_zero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_neq_f16_e32 vcc_lo, 0, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq half %arg, 0xH0000
+ %sel = select i1 %cmp, half 0xH0000, half %other
+ ret half %sel
+}
+; Should NOT be folded: f16 fcmp one with negative zero constant
+define half @fcmp_select_no_fold_one_f16_negzero(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_one_f16_negzero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0x8000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x8000
+; GFX900-NEXT: v_cmp_lg_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_one_f16_negzero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0x8000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x8000, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one half 0xH8000, %arg
+ %sel = select i1 %cmp, half %other, half 0xH8000
+ ret half %sel
+}
+
+; Should NOT be folded: f16 fcmp oeq with constant in other position
+define half @fcmp_select_no_fold_f16_other_pos(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f16_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x4248
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_eq_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f16_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0x4248, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq half %arg, 0xH4248
+ %sel = select i1 %cmp, half %other, half 0xH4248
+ ret half %sel
+}
+
+; Should NOT be folded: f16 unsupported comparison type
+define half @fcmp_select_no_fold_f16_unsupported_cmp(half %arg, half %other) {
+; GFX900-LABEL: fcmp_select_no_fold_f16_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x4248
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_gt_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_f16_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0x4248, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp olt half %arg, 0xH4248
+ %sel = select i1 %cmp, half %other, half 0xH4248
+ ret half %sel
+}
+
+;------------------------------------------------------------------------------
+; BF16 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: bfloat fcmp oeq + select with constant in true value
+define bfloat @fcmp_select_fold_oeq_bf16_imm(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_bf16_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x42480000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_bf16_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42480000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq bfloat %arg, 0xR4248
+ %sel = select i1 %cmp, bfloat 0xR4248, bfloat %other
+ ret bfloat %sel
+}
+
+; Should be folded: bfloat fcmp oeq + select with constant in true value (commutative)
+define bfloat @fcmp_select_fold_oeq_imm_bf16(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_fold_oeq_imm_bf16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x42480000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_oeq_imm_bf16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42480000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq bfloat 0xR4248, %arg
+ %sel = select i1 %cmp, bfloat 0xR4248, bfloat %other
+ ret bfloat %sel
+}
+
+; Should be folded: bfloat fcmp one + select with constant in false value
+define bfloat @fcmp_select_fold_one_bf16_imm(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_fold_one_bf16_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x40200000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_bf16_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x40200000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one bfloat %arg, 0xR4020
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xR4020
+ ret bfloat %sel
+}
+
+; Should be folded: bfloat fcmp one + select with constant in false value (commutative)
+define bfloat @fcmp_select_fold_one_imm_bf16(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_fold_one_imm_bf16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x40200000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_fold_one_imm_bf16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x40200000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one bfloat 0xR4020, %arg
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xR4020
+ ret bfloat %sel
+}
+
+; Should NOT be folded: different constants
+define bfloat @fcmp_select_no_fold_bf16_different_const(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_bf16_different_const:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x42480000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4300
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_bf16_different_const:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42480000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4300, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq bfloat %arg, 0xR4248
+ %sel = select i1 %cmp, bfloat 0xR4300, bfloat %other
+ ret bfloat %sel
+}
+
+; Should NOT be folded: NaN values bypass optimization
+define bfloat @fcmp_select_no_fold_nan_bf16(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_bf16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_bf16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, v1
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq bfloat %arg, 0xR7FC0
+ %sel = select i1 %cmp, bfloat 0xR7FC0, bfloat %other
+ ret bfloat %sel
+}
+
+; Should NOT be folded: bfloat fcmp one with NaN constant
+define bfloat @fcmp_select_no_fold_nan_bf16_one(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_nan_bf16_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, 0x7fc0
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_nan_bf16_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v0, 0x7fc0
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one bfloat %arg, 0xR7FC0
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xR7FC0
+ ret bfloat %sel
+}
+
+; Should NOT be folded: bfloat fcmp one with +Inf constant
+define bfloat @fcmp_select_no_fold_posinf_bf16_one(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_posinf_bf16_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f80
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_posinf_bf16_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x7f800000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7f80, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one bfloat %arg, 0xR7F80
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xR7F80
+ ret bfloat %sel
+}
+
+; Should NOT be folded: bfloat fcmp one with -Inf constant
+define bfloat @fcmp_select_no_fold_neginf_bf16_one(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_neginf_bf16_one:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0xff800000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0xffffff80
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_neginf_bf16_one:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0xff800000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xffffff80, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one bfloat %arg, 0xRFF80
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xRFF80
+ ret bfloat %sel
+}
+
+; Should NOT be folded: bfloat fcmp oeq with zero constant
+define bfloat @fcmp_select_no_fold_oeq_bf16_zero(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_oeq_bf16_zero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, 0, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_oeq_bf16_zero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq bfloat %arg, 0xR0000
+ %sel = select i1 %cmp, bfloat 0xR0000, bfloat %other
+ ret bfloat %sel
+}
+
+; Should NOT be folded: bfloat fcmp one with negative zero constant
+define bfloat @fcmp_select_no_fold_one_bf16_negzero(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_one_bf16_negzero:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_brev_b32 s4, 1
+; GFX900-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_one_bf16_negzero:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x80000000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xffff8000, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp one bfloat 0xR8000, %arg
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xR8000
+ ret bfloat %sel
+}
+
+; Should NOT be folded: bfloat fcmp oeq with constant in other position
+define bfloat @fcmp_select_no_fold_bf16_other_pos(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_bf16_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x42480000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_bf16_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0x42480000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp oeq bfloat %arg, 0xR4248
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xR4248
+ ret bfloat %sel
+}
+
+; Should NOT be folded: bfloat unsupported comparison type
+define bfloat @fcmp_select_no_fold_bf16_unsupported_cmp(bfloat %arg, bfloat %other) {
+; GFX900-LABEL: fcmp_select_no_fold_bf16_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: s_mov_b32 s4, 0x42480000
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
+; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: fcmp_select_no_fold_bf16_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1010-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x42480000, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = fcmp olt bfloat %arg, 0xR4248
+ %sel = select i1 %cmp, bfloat %other, bfloat 0xR4248
+ ret bfloat %sel
+}
diff --git a/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
new file mode 100644
index 0000000000000..f28d68b3b392d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
@@ -0,0 +1,975 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX1010 %s
+
+;------------------------------------------------------------------------------
+; I32 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: icmp eq + select with constant in true value
+define i32 @icmp_select_fold_eq_i32_imm(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_i32_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_i32_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %arg, 4242
+ %sel = select i1 %cmp, i32 4242, i32 %other
+ ret i32 %sel
+}
+
+; Should be folded: icmp eq + select with constant in true value (commutative)
+define i32 @icmp_select_fold_eq_imm_i32(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_imm_i32:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_imm_i32:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i32 4242, %arg
+ %sel = select i1 %cmp, i32 4242, i32 %other
+ ret i32 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value
+define i32 @icmp_select_fold_ne_i32_imm(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_i32_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_i32_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i32 %arg, 4242
+ %sel = select i1 %cmp, i32 %other, i32 4242
+ ret i32 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value (commutative)
+define i32 @icmp_select_fold_ne_imm_i32(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_imm_i32:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_imm_i32:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i32 4242, %arg
+ %sel = select i1 %cmp, i32 %other, i32 4242
+ ret i32 %sel
+}
+
+; Should NOT be folded: icmp eq with different constants
+define i32 @icmp_select_no_fold_i32_different(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i32_different:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x978
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i32_different:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x978, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %arg, 4242
+ %sel = select i1 %cmp, i32 2424, i32 %other
+ ret i32 %sel
+}
+
+; Should NOT be folded: icmp eq with constant in other position
+define i32 @icmp_select_no_fold_i32_other_pos(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i32_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i32_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %arg, 4242
+ %sel = select i1 %cmp, i32 %other, i32 4242
+ ret i32 %sel
+}
+
+; Should NOT be folded: unsupported comparison type
+define i32 @icmp_select_no_fold_i32_unsupported_cmp(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i32_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1094
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x102d
+; GFX900-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i32_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x1094, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x102d, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ugt i32 %arg, 4243
+ %sel = select i1 %cmp, i32 4141, i32 %other
+ ret i32 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i32 @icmp_select_no_fold_i32_enc_imm(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i32_enc_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i32_enc_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i32 %arg, 0
+ %sel = select i1 %cmp, i32 0, i32 %other
+ ret i32 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i32 @icmp_select_no_fold_i32_enc_imm_2(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i32_enc_imm_2:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, 64, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 64, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i32_enc_imm_2:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 64, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 64, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i32 64, %arg
+ %sel = select i1 %cmp, i32 64, i32 %other
+ ret i32 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i32 @icmp_select_no_fold_i32_enc_imm_3(i32 %arg, i32 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i32_enc_imm_3:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, -16, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, -16, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i32_enc_imm_3:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, -16, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, -16, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i32 %arg, -16
+ %sel = select i1 %cmp, i32 %other, i32 -16
+ ret i32 %sel
+}
+
+;------------------------------------------------------------------------------
+; I64 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: icmp eq + select with constant in true value
+define i64 @icmp_select_fold_eq_i64_imm(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_i64_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX900-NEXT: s_movk_i32 s5, 0x62
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_i64_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX1010-NEXT: s_movk_i32 s5, 0x62
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i64 %arg, 424242424242
+ %sel = select i1 %cmp, i64 424242424242, i64 %other
+ ret i64 %sel
+}
+
+; Should be folded: icmp eq + select with constant in true value (commutative)
+define i64 @icmp_select_fold_eq_imm_i64(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_imm_i64:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX900-NEXT: s_movk_i32 s5, 0x62
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_imm_i64:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX1010-NEXT: s_movk_i32 s5, 0x62
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i64 424242424242, %arg
+ %sel = select i1 %cmp, i64 424242424242, i64 %other
+ ret i64 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value
+define i64 @icmp_select_fold_ne_i64_imm(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_i64_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX900-NEXT: s_movk_i32 s5, 0x62
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_i64_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX1010-NEXT: s_movk_i32 s5, 0x62
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i64 %arg, 424242424242
+ %sel = select i1 %cmp, i64 %other, i64 424242424242
+ ret i64 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value (commutative)
+define i64 @icmp_select_fold_ne_imm_i64(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_imm_i64:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX900-NEXT: s_movk_i32 s5, 0x62
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_imm_i64:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX1010-NEXT: s_movk_i32 s5, 0x62
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i64 424242424242, %arg
+ %sel = select i1 %cmp, i64 %other, i64 424242424242
+ ret i64 %sel
+}
+
+; Should NOT be folded: icmp eq with different constants
+define i64 @icmp_select_no_fold_i64_different(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i64_different:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX900-NEXT: s_movk_i32 s5, 0x62
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0x719c60f8
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, 56, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i64_different:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX1010-NEXT: s_movk_i32 s5, 0x62
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x719c60f8, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 56, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i64 %arg, 424242424242
+ %sel = select i1 %cmp, i64 242424242424, i64 %other
+ ret i64 %sel
+}
+
+; Should NOT be folded: icmp eq with constant in other position
+define i64 @icmp_select_no_fold_i64_other_pos(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i64_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX900-NEXT: s_movk_i32 s5, 0x62
+; GFX900-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i64_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
+; GFX1010-NEXT: s_movk_i32 s5, 0x62
+; GFX1010-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i64 %arg, 424242424242
+ %sel = select i1 %cmp, i64 %other, i64 424242424242
+ ret i64 %sel
+}
+
+; Should NOT be folded: unsupported comparison type
+define i64 @icmp_select_no_fold_i64_unsupported_cmp(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i64_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b3
+; GFX900-NEXT: s_movk_i32 s5, 0x62
+; GFX900-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i64_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b3
+; GFX1010-NEXT: s_movk_i32 s5, 0x62
+; GFX1010-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ugt i64 %arg, 424242424242
+ %sel = select i1 %cmp, i64 424242424242, i64 %other
+ ret i64 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i64 @icmp_select_no_fold_i64_enc_imm(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i64_enc_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i64_enc_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i64 %arg, 0
+ %sel = select i1 %cmp, i64 0, i64 %other
+ ret i64 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i64 @icmp_select_no_fold_i64_enc_imm_2(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i64_enc_imm_2:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, 32, v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 32, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i64_enc_imm_2:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, 32, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 32, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i64 32, %arg
+ %sel = select i1 %cmp, i64 32, i64 %other
+ ret i64 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i64 @icmp_select_no_fold_i64_enc_imm_3(i64 %arg, i64 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i64_enc_imm_3:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, -8, v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, -8, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, -1, v3, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i64_enc_imm_3:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, -8, v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, -8, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, -1, v3, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i64 %arg, -8
+ %sel = select i1 %cmp, i64 %other, i64 -8
+ ret i64 %sel
+}
+
+;------------------------------------------------------------------------------
+; I16 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: icmp eq + select with constant in true value
+define i16 @icmp_select_fold_eq_i16_imm(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_i16_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_i16_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i16 %arg, 4242
+ %sel = select i1 %cmp, i16 4242, i16 %other
+ ret i16 %sel
+}
+
+; Should be folded: icmp eq + select with constant in true value (commutative)
+define i16 @icmp_select_fold_eq_imm_i16(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_imm_i16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_imm_i16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i16 4242, %arg
+ %sel = select i1 %cmp, i16 4242, i16 %other
+ ret i16 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value
+define i16 @icmp_select_fold_ne_i16_imm(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_i16_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_i16_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i16 %arg, 4242
+ %sel = select i1 %cmp, i16 %other, i16 4242
+ ret i16 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value (commutative)
+define i16 @icmp_select_fold_ne_imm_i16(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_imm_i16:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_imm_i16:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i16 4242, %arg
+ %sel = select i1 %cmp, i16 %other, i16 4242
+ ret i16 %sel
+}
+
+; Should NOT be folded: icmp eq with different constants
+define i16 @icmp_select_no_fold_i16_different(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i16_different:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x978
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i16_different:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x978, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i16 %arg, 4242
+ %sel = select i1 %cmp, i16 2424, i16 %other
+ ret i16 %sel
+}
+
+; Should NOT be folded: icmp eq with constant in other position
+define i16 @icmp_select_no_fold_i16_other_pos(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i16_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1092
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i16_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i16 %arg, 4242
+ %sel = select i1 %cmp, i16 %other, i16 4242
+ ret i16 %sel
+}
+
+; Should NOT be folded: unsupported comparison type
+define i16 @icmp_select_no_fold_i16_unsupported_cmp(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i16_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x1093
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
+; GFX900-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i16_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0x1093, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ugt i16 %arg, 4242
+ %sel = select i1 %cmp, i16 4242, i16 %other
+ ret i16 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i16 @icmp_select_no_fold_i16_enc_imm(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i16_enc_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i16_enc_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i16 %arg, 0
+ %sel = select i1 %cmp, i16 0, i16 %other
+ ret i16 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i16 @icmp_select_no_fold_i16_enc_imm_2(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i16_enc_imm_2:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, 45, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 45, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i16_enc_imm_2:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 45, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 45, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i16 45, %arg
+ %sel = select i1 %cmp, i16 45, i16 %other
+ ret i16 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i16 @icmp_select_no_fold_i16_enc_imm_3(i16 %arg, i16 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i16_enc_imm_3:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, -12, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, -12, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i16_enc_imm_3:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, -12, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, -12, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i16 %arg, -12
+ %sel = select i1 %cmp, i16 %other, i16 -12
+ ret i16 %sel
+}
+
+;------------------------------------------------------------------------------
+; I8 Tests
+;------------------------------------------------------------------------------
+
+; Should be folded: icmp eq + select with constant in true value
+define i8 @icmp_select_fold_eq_i8_imm(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_i8_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7b
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_i8_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i8 %arg, 123
+ %sel = select i1 %cmp, i8 123, i8 %other
+ ret i8 %sel
+}
+
+; Should be folded: icmp eq + select with constant in true value (commutative)
+define i8 @icmp_select_fold_eq_imm_i8(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_fold_eq_imm_i8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7b
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_eq_imm_i8:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i8 123, %arg
+ %sel = select i1 %cmp, i8 123, i8 %other
+ ret i8 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value
+define i8 @icmp_select_fold_ne_i8_imm(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_i8_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7b
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_i8_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i8 %arg, 123
+ %sel = select i1 %cmp, i8 %other, i8 123
+ ret i8 %sel
+}
+
+; Should be folded: icmp ne + select with constant in false value (commutative)
+define i8 @icmp_select_fold_ne_imm_i8(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_fold_ne_imm_i8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7b
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_fold_ne_imm_i8:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i8 123, %arg
+ %sel = select i1 %cmp, i8 %other, i8 123
+ ret i8 %sel
+}
+
+; Should NOT be folded: icmp eq with different constants
+define i8 @icmp_select_no_fold_i8_different(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i8_different:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7b
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7c
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i8_different:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7c, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i8 %arg, 123
+ %sel = select i1 %cmp, i8 124, i8 %other
+ ret i8 %sel
+}
+
+; Should NOT be folded: icmp eq with constant in other position
+define i8 @icmp_select_no_fold_i8_other_pos(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i8_other_pos:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7b
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX900-NEXT: v_cmp_eq_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i8_other_pos:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX1010-NEXT: v_cmp_eq_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i8 %arg, 123
+ %sel = select i1 %cmp, i8 %other, i8 123
+ ret i8 %sel
+}
+
+; Should NOT be folded: unsupported comparison type
+define i8 @icmp_select_no_fold_i8_unsupported_cmp(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i8_unsupported_cmp:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0x7c
+; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
+; GFX900-NEXT: v_cmp_lt_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i8_unsupported_cmp:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7c
+; GFX1010-NEXT: v_cmp_lt_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ugt i8 %arg, 123
+ %sel = select i1 %cmp, i8 123, i8 %other
+ ret i8 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i8 @icmp_select_no_fold_i8_enc_imm(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i8_enc_imm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i8_enc_imm:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i8 %arg, 0
+ %sel = select i1 %cmp, i8 0, i8 %other
+ ret i8 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i8 @icmp_select_no_fold_i8_enc_imm_2(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i8_enc_imm_2:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v2, 25
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, 25, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i8_enc_imm_2:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 25
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, 25, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp eq i8 25, %arg
+ %sel = select i1 %cmp, i8 25, i8 %other
+ ret i8 %sel
+}
+
+; Should NOT be folded: immediate can be encoded into cndmask
+define i8 @icmp_select_no_fold_i8_enc_imm_3(i8 %arg, i8 %other) {
+; GFX900-LABEL: icmp_select_no_fold_i8_enc_imm_3:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_movk_i32 s4, 0xfb
+; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, -5, v1, vcc
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1010-LABEL: icmp_select_no_fold_i8_enc_imm_3:
+; GFX1010: ; %bb.0: ; %entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: v_mov_b32_e32 v2, 0xfb
+; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, -5, v1, vcc_lo
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %cmp = icmp ne i8 %arg, -5
+ %sel = select i1 %cmp, i8 %other, i8 -5
+ ret i8 %sel
+}
>From 0617b6ebca4a79200d53ac45cbd3d1daa9cc6b05 Mon Sep 17 00:00:00 2001
From: Daniil Fukalov <dfukalov at gmail.com>
Date: Fri, 11 Jul 2025 13:56:58 +0200
Subject: [PATCH 2/2] [AMDGPU] Try to reuse in v_cndmask register with constant
from compare.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
For some targets, the optimization X == Const ? X : Y → X == Const ? Const : Y
can cause extra register usage or redundant immediate encoding for the constant
in cndmask generated from the ternary operation.
This patch detects such cases and reuses the register from the compare instruction
that already holds the constant, instead of materializing it again for cndmask.
The optimization avoids immediates that can be encoded into cndmask instruction
(including +-0.0), as well as !isNormal() constants.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 82 ++++++++++
.../AMDGPU/select-cmp-shared-constant-fp.ll | 152 ++++++++----------
.../AMDGPU/select-cmp-shared-constant-int.ll | 128 +++++++--------
3 files changed, 202 insertions(+), 160 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index e64d2162441ab..e49bfd166ac78 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4842,11 +4842,93 @@ AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
return SDValue();
}
+// Detect when CMP and SELECT use the same constant and fold them to avoid
+// loading the constant twice. Specifically handles patterns like:
+// %cmp = fcmp oeq float %val, 1.000000e+00
+// %sel = select i1 %cmp, float 1.000000e+00, float %other
+// It can be optimized to reuse %val instead of 1.000000e+00 in select.
+static SDValue
+foldCmpSelectWithSharedConstant(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
+ const AMDGPUSubtarget *ST) {
+ SDValue Cond = N->getOperand(0);
+ SDValue TrueVal = N->getOperand(1);
+ SDValue FalseVal = N->getOperand(2);
+
+ // Check if condition is a comparison.
+ if (Cond.getOpcode() != ISD::SETCC)
+ return SDValue();
+
+ SDValue LHS = Cond.getOperand(0);
+ SDValue RHS = Cond.getOperand(1);
+ ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
+
+ bool isFloatingPoint = LHS.getValueType().isFloatingPoint();
+ bool isInteger = LHS.getValueType().isInteger();
+
+ // Handle simple floating-point and integer types only.
+ if (!isFloatingPoint && !isInteger)
+ return SDValue();
+
+ bool isEquality = CC == (isFloatingPoint ? ISD::SETOEQ : ISD::SETEQ);
+ bool isNonEquality = CC == (isFloatingPoint ? ISD::SETONE : ISD::SETNE);
+ if (!isEquality && !isNonEquality)
+ return SDValue();
+
+ SDValue ArgVal, ConstVal;
+ if ((isFloatingPoint && isa<ConstantFPSDNode>(RHS)) ||
+ (isInteger && isa<ConstantSDNode>(RHS))) {
+ ConstVal = RHS;
+ ArgVal = LHS;
+ } else if ((isFloatingPoint && isa<ConstantFPSDNode>(LHS)) ||
+ (isInteger && isa<ConstantSDNode>(LHS))) {
+ ConstVal = LHS;
+ ArgVal = RHS;
+ } else {
+ return SDValue();
+ }
+
+ // Check if constant should not be optimized - early return if not.
+ if (isFloatingPoint) {
+ const APFloat &Val = cast<ConstantFPSDNode>(ConstVal)->getValueAPF();
+ const GCNSubtarget *GCNST = static_cast<const GCNSubtarget *>(ST);
+
+ // Only optimize normal floating-point values, skip optimization for
+ // inlinable floating-point constants.
+ if (!Val.isNormal() || GCNST->getInstrInfo()->isInlineConstant(Val))
+ return SDValue();
+ } else {
+ int64_t IntVal = cast<ConstantSDNode>(ConstVal)->getSExtValue();
+
+ // Skip optimization for inlinable integer immediates.
+ // Inlinable immediates include: -16 to 64 (inclusive).
+ if (IntVal >= -16 && IntVal <= 64)
+ return SDValue();
+ }
+
+ // For equality and non-equality comparisons, patterns:
+ // select (setcc x, const), const, y -> select (setcc x, const), x, y
+ // select (setccinv x, const), y, const -> select (setccinv x, const), y, x
+ if (!(isEquality && TrueVal == ConstVal) &&
+ !(isNonEquality && FalseVal == ConstVal))
+ return SDValue();
+
+ SDValue SelectLHS = (isEquality && TrueVal == ConstVal) ? ArgVal : TrueVal;
+ SDValue SelectRHS =
+ (isNonEquality && FalseVal == ConstVal) ? ArgVal : FalseVal;
+ return DCI.DAG.getNode(ISD::SELECT, SDLoc(N), N->getValueType(0), Cond,
+ SelectLHS, SelectRHS);
+}
+
SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
return Folded;
+ // Try to fold CMP + SELECT patterns with shared constants (both FP and
+ // integer).
+ if (SDValue Folded = foldCmpSelectWithSharedConstant(N, DCI, Subtarget))
+ return Folded;
+
SDValue Cond = N->getOperand(0);
if (Cond.getOpcode() != ISD::SETCC)
return SDValue();
diff --git a/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
index 14f04a8ca05fd..11af704d30973 100644
--- a/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
@@ -15,16 +15,15 @@ define float @fcmp_select_fold_oeq_f32_imm(float %arg, float %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0x42487ed8
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x42487ed8
-; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_f32_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42487ed8, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x42487ed8, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0x42487ed8, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq float %arg, 0x40490FDB00000000
@@ -38,16 +37,15 @@ define float @fcmp_select_fold_oeq_imm_f32(float %arg, float %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0x42487ed8
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x42487ed8
-; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_imm_f32:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42487ed8, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x42487ed8, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0x42487ed8, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq float 0x40490FDB00000000, %arg
@@ -61,16 +59,15 @@ define float @fcmp_select_fold_one_f32_imm(float %arg, float %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0x402df850
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x402df850
; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_one_f32_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x402df850, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x402df850, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one float %arg, 0x4005BF0A00000000
@@ -84,16 +81,15 @@ define float @fcmp_select_fold_one_imm_f32(float %arg, float %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0x402df850
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x402df850
; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_one_imm_f32:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x402df850, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x402df850, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one float 0x4005BF0A00000000, %arg
@@ -355,11 +351,9 @@ define double @fcmp_select_fold_oeq_f64_imm(double %arg, double %other) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0x54442d18
; GFX900-NEXT: s_mov_b32 s5, 0x400921fb
-; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x54442d18
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x400921fb
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: v_cmp_eq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_f64_imm:
@@ -367,9 +361,9 @@ define double @fcmp_select_fold_oeq_f64_imm(double %arg, double %other) {
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: s_mov_b32 s4, 0x54442d18
; GFX1010-NEXT: s_mov_b32 s5, 0x400921fb
-; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x54442d18, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x400921fb, v3, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq double %arg, 3.141592653589793
@@ -383,11 +377,9 @@ define double @fcmp_select_fold_oeq_imm_f64(double %arg, double %other) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0x54442d18
; GFX900-NEXT: s_mov_b32 s5, 0x400921fb
-; GFX900-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x54442d18
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x400921fb
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: v_cmp_eq_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_imm_f64:
@@ -395,9 +387,9 @@ define double @fcmp_select_fold_oeq_imm_f64(double %arg, double %other) {
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: s_mov_b32 s4, 0x54442d18
; GFX1010-NEXT: s_mov_b32 s5, 0x400921fb
-; GFX1010-NEXT: v_cmp_neq_f64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x54442d18, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x400921fb, v3, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_f64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq double 3.141592653589793, %arg
@@ -413,9 +405,7 @@ define double @fcmp_select_fold_one_f64_imm(double %arg, double %other) {
; GFX900-NEXT: s_mov_b32 s4, 0x8b145769
; GFX900-NEXT: s_mov_b32 s5, 0x4005bf0a
; GFX900-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x8b145769
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x4005bf0a
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -425,8 +415,8 @@ define double @fcmp_select_fold_one_f64_imm(double %arg, double %other) {
; GFX1010-NEXT: s_mov_b32 s4, 0x8b145769
; GFX1010-NEXT: s_mov_b32 s5, 0x4005bf0a
; GFX1010-NEXT: v_cmp_lg_f64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x8b145769, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x4005bf0a, v3, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one double %arg, 2.718281828459045
@@ -441,9 +431,7 @@ define double @fcmp_select_fold_one_imm_f64(double %arg, double %other) {
; GFX900-NEXT: s_mov_b32 s4, 0x8b145769
; GFX900-NEXT: s_mov_b32 s5, 0x4005bf0a
; GFX900-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x8b145769
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x4005bf0a
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -453,8 +441,8 @@ define double @fcmp_select_fold_one_imm_f64(double %arg, double %other) {
; GFX1010-NEXT: s_mov_b32 s4, 0x8b145769
; GFX1010-NEXT: s_mov_b32 s5, 0x4005bf0a
; GFX1010-NEXT: v_cmp_lg_f64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x8b145769, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x4005bf0a, v3, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one double 2.718281828459045, %arg
@@ -852,16 +840,15 @@ define half @fcmp_select_fold_oeq_f16_imm(half %arg, half %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x4248
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
-; GFX900-NEXT: v_cmp_neq_f16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_f16_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_neq_f16_e32 vcc_lo, 0x4248, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0x4248, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq half %arg, 0xH4248
@@ -875,16 +862,15 @@ define half @fcmp_select_fold_oeq_imm_f16(half %arg, half %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x4248
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
-; GFX900-NEXT: v_cmp_neq_f16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_f16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_imm_f16:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_neq_f16_e32 vcc_lo, 0x4248, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0x4248, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq half 0xH4248, %arg
@@ -898,16 +884,15 @@ define half @fcmp_select_fold_one_f16_imm(half %arg, half %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x4020
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
; GFX900-NEXT: v_cmp_lg_f16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_one_f16_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0x4020, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one half %arg, 0xH4020
@@ -921,16 +906,15 @@ define half @fcmp_select_fold_one_imm_f16(half %arg, half %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x4020
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
; GFX900-NEXT: v_cmp_lg_f16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_one_imm_f16:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0x4020, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one half 0xH4020, %arg
@@ -1142,19 +1126,18 @@ define bfloat @fcmp_select_fold_oeq_bf16_imm(bfloat %arg, bfloat %other) {
; GFX900-LABEL: fcmp_select_fold_oeq_bf16_imm:
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX900-NEXT: s_mov_b32 s4, 0x42480000
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
-; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, s4, v2
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_bf16_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42480000, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX1010-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0x42480000, v2
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq bfloat %arg, 0xR4248
@@ -1167,19 +1150,18 @@ define bfloat @fcmp_select_fold_oeq_imm_bf16(bfloat %arg, bfloat %other) {
; GFX900-LABEL: fcmp_select_fold_oeq_imm_bf16:
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX900-NEXT: s_mov_b32 s4, 0x42480000
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4248
-; GFX900-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, s4, v2
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_oeq_imm_bf16:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1010-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0x42480000, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4248, v1, vcc_lo
+; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX1010-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0x42480000, v2
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp oeq bfloat 0xR4248, %arg
@@ -1192,19 +1174,18 @@ define bfloat @fcmp_select_fold_one_bf16_imm(bfloat %arg, bfloat %other) {
; GFX900-LABEL: fcmp_select_fold_one_bf16_imm:
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX900-NEXT: s_mov_b32 s4, 0x40200000
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
-; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v2
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_one_bf16_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x40200000, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x40200000, v2
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one bfloat %arg, 0xR4020
@@ -1217,19 +1198,18 @@ define bfloat @fcmp_select_fold_one_imm_bf16(bfloat %arg, bfloat %other) {
; GFX900-LABEL: fcmp_select_fold_one_imm_bf16:
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX900-NEXT: s_mov_b32 s4, 0x40200000
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x4020
-; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_lg_f32_e32 vcc, s4, v2
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: fcmp_select_fold_one_imm_bf16:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x40200000, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x4020, v1, vcc_lo
+; GFX1010-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX1010-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0x40200000, v2
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = fcmp one bfloat 0xR4020, %arg
diff --git a/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
index f28d68b3b392d..4383cfd36f945 100644
--- a/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
@@ -12,16 +12,15 @@ define i32 @icmp_select_fold_eq_i32_imm(i32 %arg, i32 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
-; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_i32_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i32 %arg, 4242
@@ -35,16 +34,15 @@ define i32 @icmp_select_fold_eq_imm_i32(i32 %arg, i32 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
-; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_imm_i32:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i32 4242, %arg
@@ -58,16 +56,15 @@ define i32 @icmp_select_fold_ne_i32_imm(i32 %arg, i32 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_ne_i32_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i32 %arg, 4242
@@ -81,16 +78,15 @@ define i32 @icmp_select_fold_ne_imm_i32(i32 %arg, i32 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
; GFX900-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_ne_imm_i32:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i32 4242, %arg
@@ -241,11 +237,9 @@ define i64 @icmp_select_fold_eq_i64_imm(i64 %arg, i64 %other) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX900-NEXT: s_movk_i32 s5, 0x62
-; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_i64_imm:
@@ -253,9 +247,9 @@ define i64 @icmp_select_fold_eq_i64_imm(i64 %arg, i64 %other) {
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX1010-NEXT: s_movk_i32 s5, 0x62
-; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i64 %arg, 424242424242
@@ -270,11 +264,9 @@ define i64 @icmp_select_fold_eq_imm_i64(i64 %arg, i64 %other) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX900-NEXT: s_movk_i32 s5, 0x62
-; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_imm_i64:
@@ -282,9 +274,9 @@ define i64 @icmp_select_fold_eq_imm_i64(i64 %arg, i64 %other) {
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX1010-NEXT: s_movk_i32 s5, 0x62
-; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i64 424242424242, %arg
@@ -300,9 +292,7 @@ define i64 @icmp_select_fold_ne_i64_imm(i64 %arg, i64 %other) {
; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX900-NEXT: s_movk_i32 s5, 0x62
; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -312,8 +302,8 @@ define i64 @icmp_select_fold_ne_i64_imm(i64 %arg, i64 %other) {
; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX1010-NEXT: s_movk_i32 s5, 0x62
; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i64 %arg, 424242424242
@@ -329,9 +319,7 @@ define i64 @icmp_select_fold_ne_imm_i64(i64 %arg, i64 %other) {
; GFX900-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX900-NEXT: s_movk_i32 s5, 0x62
; GFX900-NEXT: v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 v4, 0xc6d1a9b2
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x62
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -341,8 +329,8 @@ define i64 @icmp_select_fold_ne_imm_i64(i64 %arg, i64 %other) {
; GFX1010-NEXT: s_mov_b32 s4, 0xc6d1a9b2
; GFX1010-NEXT: s_movk_i32 s5, 0x62
; GFX1010-NEXT: v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0xc6d1a9b2, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, 0x62, v3, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i64 424242424242, %arg
@@ -515,16 +503,15 @@ define i16 @icmp_select_fold_eq_i16_imm(i16 %arg, i16 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
-; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_i16_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i16 %arg, 4242
@@ -538,16 +525,15 @@ define i16 @icmp_select_fold_eq_imm_i16(i16 %arg, i16 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
-; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, s4, v0
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_imm_i16:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x1092, v0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i16 4242, %arg
@@ -561,16 +547,15 @@ define i16 @icmp_select_fold_ne_i16_imm(i16 %arg, i16 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_ne_i16_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i16 %arg, 4242
@@ -584,16 +569,15 @@ define i16 @icmp_select_fold_ne_imm_i16(i16 %arg, i16 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x1092
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x1092
; GFX900-NEXT: v_cmp_ne_u16_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_ne_imm_i16:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x1092, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x1092, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i16 4242, %arg
@@ -743,17 +727,16 @@ define i8 @icmp_select_fold_eq_i8_imm(i8 %arg, i8 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x7b
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
-; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_i8_imm:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
-; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i8 %arg, 123
@@ -767,17 +750,16 @@ define i8 @icmp_select_fold_eq_imm_i8(i8 %arg, i8 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x7b
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
-; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cmp_eq_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_eq_imm_i8:
; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
-; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp eq i8 123, %arg
@@ -791,9 +773,8 @@ define i8 @icmp_select_fold_ne_i8_imm(i8 %arg, i8 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x7b
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_ne_i8_imm:
@@ -801,7 +782,7 @@ define i8 @icmp_select_fold_ne_i8_imm(i8 %arg, i8 %other) {
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i8 %arg, 123
@@ -815,9 +796,8 @@ define i8 @icmp_select_fold_ne_imm_i8(i8 %arg, i8 %other) {
; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_movk_i32 s4, 0x7b
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x7b
; GFX900-NEXT: v_cmp_ne_u16_sdwa vcc, v0, s4 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX1010-LABEL: icmp_select_fold_ne_imm_i8:
@@ -825,7 +805,7 @@ define i8 @icmp_select_fold_ne_imm_i8(i8 %arg, i8 %other) {
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: v_mov_b32_e32 v2, 0x7b
; GFX1010-NEXT: v_cmp_ne_u16_sdwa vcc_lo, v0, v2 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, 0x7b, v1, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX1010-NEXT: s_setpc_b64 s[30:31]
entry:
%cmp = icmp ne i8 123, %arg
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