[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

> > Is it possible to write this as a post legalisation DAG combine? to remove the need for dedicated isel patterns.
> 
> Do you mean a pattern that combines stores whenever the source is a `fp_to_sint`, or the other way around?

I was thinking the former.  There's already a combine to handle the case where the source is `ISD::EXTRACT_VECTOR_ELT` and was wondering if you could convert the scalar `fp_to_sint` to a vector one and then the existing combine would then convert the store to floating point. This might be easier said than done as we've tripped over this before for the SME streaming mode case but I'm hoping that logic can be reused here.

https://github.com/llvm/llvm-project/pull/147707