[llvm] [AMDGPU][SDAG] Support source modifiers on select integer operands (PR #147325)

[Chris Jackson via llvm-commits]

chrisjbris wrote:

So what's happening here is, after the source modifier folding for the select has occurred, the combiner later produces:
```
Combining: t17: i64 = xor # D:1 t14, Constant:i64<-9223372036854775808>
Creating new node: t51: v2i32 = bitcast # D:1 t14
Creating new node: t52: i32 = extract_vector_elt # D:1 t51, Constant:i32<0>
Creating new node: t53: i32 = extract_vector_elt # D:1 t51, Constant:i32<1>
Creating constant: t54: i32 = Constant<-2147483648>
Creating new node: t55: i32 = xor # D:1 t53, Constant:i32<-2147483648>
Creating new node: t56: v2i32 = BUILD_VECTOR # D:1 t52, t55
Creating new node: t57: i64 = bitcast # D:1 t56
```
Presumably a realisation the only the high value of the xor operands are significant.
Later this i32 xor node is passed into DAGCombiner::foldBitcastedFPLogic() which creates:
```
Creating new node: t58: f32 = bitcast # D:1 t53
Creating new node: t59: f32 = fneg # D:1 t58
```
Resulting in fneg being applied twice. Hence, the vgpr in the fneg i64 test cases are not negated.

https://github.com/llvm/llvm-project/pull/147325