[llvm] [RISCV] Improve hasAllNBitUsers for SLLIW. (PR #148344)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/148344.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp (+9-1) 
- (modified) llvm/test/CodeGen/RISCV/sextw-removal.ll (+1-2) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index d257f56cf4129..d8570d5d2b211 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -158,7 +158,6 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
       case RISCV::MULW:
       case RISCV::REMUW:
       case RISCV::REMW:
-      case RISCV::SLLIW:
       case RISCV::SLLW:
       case RISCV::SRAIW:
       case RISCV::SRAW:
@@ -188,6 +187,7 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
         if (Bits >= 32)
           break;
         return false;
+
       case RISCV::SEXT_B:
       case RISCV::PACKH:
         if (Bits >= 8)
@@ -228,6 +228,14 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
         Worklist.push_back(std::make_pair(UserMI, Bits + ShAmt));
         break;
       }
+      case RISCV::SLLIW: {
+        unsigned ShAmt = UserMI->getOperand(2).getImm();
+        if (Bits >= 32 - ShAmt)
+          break;
+        Worklist.push_back(std::make_pair(UserMI, Bits + ShAmt));
+        break;
+      }
+
       case RISCV::ANDI: {
         uint64_t Imm = UserMI->getOperand(2).getImm();
         if (Bits >= (unsigned)llvm::bit_width(Imm))
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index 9c8230572b926..b128abb6b5bdd 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1532,10 +1532,9 @@ define signext i32 @test21(i64 %arg1, i64 %arg2, i64 %arg3)  {
 ; RV64I-NEXT:    andi a0, a0, 1104
 ; RV64I-NEXT:    or a0, a0, a6
 ; RV64I-NEXT:    addi a2, a2, 1
-; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    addw a0, a0, a1
 ; RV64I-NEXT:    bltu a2, a5, .LBB25_1
 ; RV64I-NEXT:  # %bb.2: # %bb7
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: test21:

``````````

</details>


https://github.com/llvm/llvm-project/pull/148344