[llvm] d0a0a1a - [RISCV] Remove unneeded AddedComplexity from Xqcibi patterns. NFCI (#148301)

[via llvm-commits]

Author: Craig Topper
Date: 2025-07-11T22:16:38-07:00
New Revision: d0a0a1ae638fb99ae4fe9f1c4082dbe5a560ec0a

URL: https://github.com/llvm/llvm-project/commit/d0a0a1ae638fb99ae4fe9f1c4082dbe5a560ec0a
DIFF: https://github.com/llvm/llvm-project/commit/d0a0a1ae638fb99ae4fe9f1c4082dbe5a560ec0a.diff

LOG: [RISCV] Remove unneeded AddedComplexity from Xqcibi patterns. NFCI (#148301)

We don't have any tests that show why this AddedComplexity is needed.
ImmLeafs are automatically ranked higher than register operands so there
is no ambgiuity with the base ISA here.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 7cc7f380c3f69..add54a7da09cb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1417,7 +1417,7 @@ def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
 
 /// Branches
 
-let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2 in {
+let Predicates = [HasVendorXqcibi, IsRV32] in {
 def : BcciPat<SETEQ, QC_BEQI, simm5nonzero>;
 def : BcciPat<SETNE, QC_BNEI, simm5nonzero>;
 def : BcciPat<SETLT, QC_BLTI, simm5nonzero>;
@@ -1445,7 +1445,7 @@ def : SelectQCbi<SETLT, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>
 def : SelectQCbi<SETGE, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
 def : SelectQCbi<SETULT, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
 def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
-} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
+} // let Predicates = [HasVendorXqcibi, IsRV32]
 
 let Predicates = [HasVendorXqcibm, IsRV32] in {
 def : Pat<(sext_inreg (i32 GPR:$rs1), i1), (QC_EXT GPR:$rs1, 1, 0)>;