[llvm] [RISCV] Add ISel patterns for Xqciac QC_SHLADD instruction (PR #148256)

[Sudharsan Veeravalli via llvm-commits]

================
@@ -1359,6 +1359,12 @@ class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
 let Predicates = [HasVendorXqciac, IsRV32] in {
 def : Pat<(XLenVT (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))),
           (QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>;
+foreach i = 4-31 in {
----------------
svs-quic wrote:

The pattern is:

```
def : Pat<(i32 (add  GPRNoX0:$rs1, (shl GPRNoX0:$rs2, uimm5gt3:$imm))),
          (QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, $imm)>;

```
Before ISel begins:

```
Optimized legalized selection DAG: %bb.0 'pow2:entry'
SelectionDAG has 11 nodes:
  t0: ch,glue = EntryToken
        t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t12: i32 = shl t4, Constant:i32<5>
      t2: i32,ch = CopyFromReg t0, Register:i32 %0
    t7: i32 = add nsw t12, t2
  t9: ch,glue = CopyToReg t0, Register:i32 $x10, t7
  t10: ch = RISCVISD::RET_GLUE t9, Register:i32 $x10, t9:1


===== Instruction selection begins: %bb.0 'entry'
```

ISEL:

```
ISEL: Starting selection on root node: t7: i32 = add nsw t12, t2
ISEL: Starting pattern match
.....
  Match failed at index 40393
  Continuing at 40857
  Match failed at index 40868
  Continuing at 40916
  Match failed at index 40919
  Continuing at 40974
  Match failed at index 40976
  Continuing at 41019
  Match failed at index 41021
  Continuing at 41107
  Continuing at 41108
  OpcodeSwitch from 41110 to 41156
  TypeSwitch[i32] from 41164 to 41183
  Morphed node: t7: i32 = QC_SHLADD nsw t2, t4, Constant:i32<5>
ISEL: Match complete!
```
After ISEL:

```
===== Instruction selection ends:

Selected selection DAG: %bb.0 'pow2:entry'
SelectionDAG has 12 nodes:
  t0: ch,glue = EntryToken
      t2: i32,ch = CopyFromReg t0, Register:i32 %0
      t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t15: i32 = ADDI Register:i32 $x0, TargetConstant:i32<5>
    t7: i32 = QC_SHLADD nsw t2, t4, t15
  t9: ch,glue = CopyToReg t0, Register:i32 $x10, t7
  t10: ch = PseudoRET Register:i32 $x10, t9, t9:1
```

```
*** MachineFunction at end of ISel ***
# Machine code for function pow2: IsSSA, TracksLiveness
Function Live Ins: $x10 in %0, $x11 in %1

bb.0.entry:
  liveins: $x10, $x11
  %1:gprnox0 = COPY $x11
  %0:gprnox0 = COPY $x10
  %2:gpr = ADDI $x0, 5
  %3:gprnox0 = nsw QC_SHLADD %0:gprnox0, %1:gprnox0, killed %2:gpr
  $x10 = COPY %3:gprnox0
  PseudoRET implicit $x10

# End machine code for function pow2.
```


https://github.com/llvm/llvm-project/pull/148256