[llvm] [RISCV] Add ISel patterns for Xqciac QC_SHLADD instruction (PR #148256)

[Sudharsan Veeravalli via llvm-commits]

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@@ -1359,6 +1359,12 @@ class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
 let Predicates = [HasVendorXqciac, IsRV32] in {
 def : Pat<(XLenVT (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))),
           (QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>;
+foreach i = 4-31 in {
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svs-quic wrote:

Yeah I agree. When I use the ImmLeaf the ISD::Constant on SHL does not get converted into a ISD::TargetConstant and as a result the compiler is turning the ISD::Constant into an ADDI x0, <imm> and converting the QC_SHLADD to something like 

li a2, imm
QC_SHLADD a0,a0,a1,a2

which is incorrect.

I'm working on fixing this.

https://github.com/llvm/llvm-project/pull/148256