[llvm] [RISCV] Support PreserveMost calling convention (PR #148214)

[Sam Elliott via llvm-commits]

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@@ -413,6 +413,8 @@ added in the future:
     - On AArch64 the callee preserve all general purpose registers, except
       X0-X8 and X16-X18. Not allowed with ``nest``.
 
+    - On RISC-V the callee preserve x5-x31 registers.
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lenary wrote:

This isn't going to work as the PLT stub can/does clobber some temporary registers (and exactly which depend on a lot of things). This is why AArch64 does not preserve x16-x18.

https://github.com/llvm/llvm-project/pull/148214