[llvm] [ISel] Commute FMUL and inserting zero into vector lane (PR #146096)
Julian Nagele via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 11 10:17:32 PDT 2025
https://github.com/juliannagele updated https://github.com/llvm/llvm-project/pull/146096
>From 93a6be03b51027e351458382ff8c05e65fbacbef Mon Sep 17 00:00:00 2001
From: Julian Nagele <j.nagele at apple.com>
Date: Fri, 27 Jun 2025 15:32:18 +0100
Subject: [PATCH 1/3] Add test for inserting zero into vector lane of fmul
result
---
llvm/test/CodeGen/AArch64/arm64-vmul.ll | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index 937a17ca6c1e0..27c5668b06d02 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -1186,6 +1186,16 @@ define double @fmul_lane_d(double %A, <2 x double> %vec) nounwind {
ret double %res
}
+define <4 x float> @fmul_insert_zero(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: fmul_insert_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmul.4s v0, v0, v1
+; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: ret
+ %mul = fmul <4 x float> %A, %B
+ %mul_set_lane = insertelement <4 x float> %mul, float 0.000000e+00, i64 3
+ ret <4 x float> %mul_set_lane
+}
define <2 x float> @fmulx_lane_2s(<2 x float> %A, <2 x float> %B) nounwind {
>From e08422d223607519aeb742e774b180b148930d02 Mon Sep 17 00:00:00 2001
From: Julian Nagele <j.nagele at apple.com>
Date: Fri, 27 Jun 2025 15:39:14 +0100
Subject: [PATCH 2/3] [ISel] Commute FMUL and inserting zero into vector lane
---
.../Target/AArch64/AArch64ISelLowering.cpp | 32 +++++++++++++++++++
llvm/test/CodeGen/AArch64/arm64-vmul.ll | 2 +-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c8b1eafd35495..867833f67b822 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -26268,11 +26268,43 @@ static SDValue removeRedundantInsertVectorElt(SDNode *N) {
return ExtractVec;
}
+static SDValue commuteInsertVectorEltFMul(SDNode *N, SelectionDAG &DAG) {
+ assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && "Unexpected node!");
+ SDValue InsertVec = N->getOperand(0);
+ SDValue InsertVal = N->getOperand(1);
+ SDValue InsertIdx = N->getOperand(2);
+
+ // Only handle constant 0 insertion...
+ if (!(isNullConstant(InsertVal) || isNullFPConstant(InsertVal)))
+ return SDValue();
+ // ... into the result of an FMUL.
+ if (InsertVec.getOpcode() != ISD::FMUL)
+ return SDValue();
+
+ // Insert into the operand of FMUL instead.
+ SDValue FMulOp = InsertVec.getOperand(0);
+
+ if (!InsertVec.hasOneUse() || !FMulOp.hasOneUse())
+ return SDValue();
+
+ SDValue InsertOp =
+ DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), FMulOp.getValueType(),
+ FMulOp, InsertVal, InsertIdx);
+ SDValue FMul =
+ DAG.getNode(ISD::FMUL, SDLoc(InsertVec), InsertVec.getValueType(),
+ InsertOp, InsertVec.getOperand(1));
+ DAG.ReplaceAllUsesWith(N, &FMul);
+ return FMul;
+}
+
static SDValue
performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
if (SDValue Res = removeRedundantInsertVectorElt(N))
return Res;
+ if (SDValue Res = commuteInsertVectorEltFMul(N, DCI.DAG))
+ return Res;
+
return performPostLD1Combine(N, DCI, true);
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index 27c5668b06d02..1e33f81b9b835 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -1189,8 +1189,8 @@ define double @fmul_lane_d(double %A, <2 x double> %vec) nounwind {
define <4 x float> @fmul_insert_zero(<4 x float> %A, <4 x float> %B) {
; CHECK-LABEL: fmul_insert_zero:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmul.4s v0, v0, v1
; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: fmul.4s v0, v0, v1
; CHECK-NEXT: ret
%mul = fmul <4 x float> %A, %B
%mul_set_lane = insertelement <4 x float> %mul, float 0.000000e+00, i64 3
>From e3b38a9faff4ab3cd76506720f5d81e64b3bb871 Mon Sep 17 00:00:00 2001
From: Julian Nagele <j.nagele at apple.com>
Date: Fri, 11 Jul 2025 18:13:12 +0100
Subject: [PATCH 3/3] fixup! [ISel] Commute FMUL and inserting zero into vector
lane
---
.../Target/AArch64/AArch64ISelLowering.cpp | 16 ++++++---
llvm/test/CodeGen/AArch64/arm64-vmul.ll | 36 +++++++++++++++++++
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 867833f67b822..bb32ef5e13c10 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -26283,16 +26283,24 @@ static SDValue commuteInsertVectorEltFMul(SDNode *N, SelectionDAG &DAG) {
// Insert into the operand of FMUL instead.
SDValue FMulOp = InsertVec.getOperand(0);
+ SDValue FMulOp2 = InsertVec.getOperand(1);
- if (!InsertVec.hasOneUse() || !FMulOp.hasOneUse())
+ if (!InsertVec.hasOneUse())
return SDValue();
+ if (!InsertVec->isOnlyUserOf(FMulOp.getNode())) {
+ if (!InsertVec->isOnlyUserOf(FMulOp2.getNode()))
+ return SDValue();
+ std::swap(FMulOp, FMulOp2);
+ }
+
SDValue InsertOp =
DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), FMulOp.getValueType(),
FMulOp, InsertVal, InsertIdx);
- SDValue FMul =
- DAG.getNode(ISD::FMUL, SDLoc(InsertVec), InsertVec.getValueType(),
- InsertOp, InsertVec.getOperand(1));
+ if (FMulOp == FMulOp2)
+ FMulOp2 = InsertOp;
+ SDValue FMul = DAG.getNode(ISD::FMUL, SDLoc(InsertVec),
+ InsertVec.getValueType(), InsertOp, FMulOp2);
DAG.ReplaceAllUsesWith(N, &FMul);
return FMul;
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index 1e33f81b9b835..9f48cb788d5d2 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -1197,6 +1197,42 @@ define <4 x float> @fmul_insert_zero(<4 x float> %A, <4 x float> %B) {
ret <4 x float> %mul_set_lane
}
+define <4 x float> @fmul_insert_zero_same(<4 x float> %A) {
+; CHECK-LABEL: fmul_insert_zero_same:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: fmul.4s v0, v0, v0
+; CHECK-NEXT: ret
+ %mul = fmul <4 x float> %A, %A
+ %mul_set_lane = insertelement <4 x float> %mul, float 0.000000e+00, i64 3
+ ret <4 x float> %mul_set_lane
+}
+
+define <4 x float> @fmul_insert_zero1(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+; CHECK-LABEL: fmul_insert_zero1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fsub.4s v0, v2, v0
+; CHECK-NEXT: mov.s v1[3], wzr
+; CHECK-NEXT: fmul.4s v0, v1, v0
+; CHECK-NEXT: ret
+ %sub = fsub <4 x float> %C, %A
+ %mul = fmul <4 x float> %B, %sub
+ %mul_set_lane = insertelement <4 x float> %mul, float 0.000000e+00, i64 3
+ ret <4 x float> %mul_set_lane
+}
+
+define <4 x float> @fmul_insert_zero2(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: fmul_insert_zero2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov.s v0[3], wzr
+; CHECK-NEXT: fmul.4s v0, v0, v1
+; CHECK-NEXT: fsub.4s v0, v1, v0
+; CHECK-NEXT: ret
+ %mul = fmul <4 x float> %B, %A
+ %mul_set_lane = insertelement <4 x float> %mul, float 0.000000e+00, i64 3
+ %sub = fsub <4 x float> %B, %mul_set_lane
+ ret <4 x float> %sub
+}
define <2 x float> @fmulx_lane_2s(<2 x float> %A, <2 x float> %B) nounwind {
; CHECK-LABEL: fmulx_lane_2s:
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