[llvm] [AMDGPU][SDAG] Support source modifiers on select integer operands (PR #147325)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 11 07:58:13 PDT 2025


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
``````````

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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index ef2e9c25f..b8f940b82 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4940,13 +4940,13 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
             SrcModTrue ? SrcModTrue.getValueType() : SrcModFalse.getValueType();
         SDValue FLHS =
             SrcModTrue ? SrcModTrue : DAG.getNode(ISD::BITCAST, SL, FVT, LHS);
-        SDValue FRHS = SrcModFalse ? SrcModFalse
-                                   : DAG.getNode(ISD::BITCAST, SL, FVT, RHS);
+        SDValue FRHS =
+            SrcModFalse ? SrcModFalse : DAG.getNode(ISD::BITCAST, SL, FVT, RHS);
         SDValue FSelect = DAG.getNode(ISD::SELECT, SL, FVT, Cond, FLHS, FRHS);
         return DAG.getNode(ISD::BITCAST, SL, VT, FSelect);
-    }
-    return SDValue();
-  };
+      }
+      return SDValue();
+    };
 
     // Support source modifiers on integer operands.
     if (VT == MVT::i32 || VT == MVT::v2i32)
@@ -5036,7 +5036,7 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
         return Res;
       }
     }
-}
+  }
 
   // There's no reason to not do this if the condition has other uses.
   return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);

``````````

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https://github.com/llvm/llvm-project/pull/147325


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