[llvm] [DAG] SelectionDAG::canCreateUndefOrPoison - Mark AVGFLOORS and AVGCE… (PR #148191)

[via llvm-commits]

https://github.com/aabhinavg1 created https://github.com/llvm/llvm-project/pull/148191

…ILS as safe

This patch updates `SelectionDAG::canCreateUndefOrPoison` to indicate that `ISD::AVGFLOORS` and `ISD::AVGCEILS` do not introduce poison or undef values.

This is formally verified using Alive2:
- AVGFLOORS: https://alive2.llvm.org/ce/z/JWZcNr
- AVGCEILS: https://alive2.llvm.org/ce/z/cW3jrR

These patterns are safe due to the use of `sext i8` into `i32`, which ensures no signed overflow occurs. The arithmetic is done in the wider domain before truncating safely back to `i8`.

Includes test coverage to ensure correctness.

Differential Revision: <fill this after uploading to Phabricator or GH>

>From 3e3632e6db4fd499d14485df70e6cf5069b99aa1 Mon Sep 17 00:00:00 2001
From: aabhinavg1 <tiwariabhinavak at gmail.com>
Date: Fri, 11 Jul 2025 15:56:53 +0530
Subject: [PATCH] [DAG] SelectionDAG::canCreateUndefOrPoison - Mark AVGFLOORS
 and AVGCEILS as safe

This patch updates `SelectionDAG::canCreateUndefOrPoison` to indicate that
`ISD::AVGFLOORS` and `ISD::AVGCEILS` do not introduce poison or undef values.

This is formally verified using Alive2:
- AVGFLOORS: https://alive2.llvm.org/ce/z/JWZcNr
- AVGCEILS: https://alive2.llvm.org/ce/z/cW3jrR

These patterns are safe due to the use of `sext i8` into `i32`, which ensures
no signed overflow occurs. The arithmetic is done in the wider domain before
truncating safely back to `i8`.

Includes test coverage to ensure correctness.

Differential Revision: <fill this after uploading to Phabricator or GH>
---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |  4 ++++
 llvm/test/CodeGen/AArch64/avgfloor-u8.ll       | 16 ++++++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/avgfloor-u8.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c1356239ad206..78f00809e3862 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5542,6 +5542,10 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::UADDSAT:
   case ISD::SSUBSAT:
   case ISD::USUBSAT:
+  case ISD::AVGFLOORS:
+  case ISD::AVGFLOORU:
+  case ISD::AVGCEILS:
+  case ISD::AVGCEILU:
   case ISD::MULHU:
   case ISD::MULHS:
   case ISD::SMIN:
diff --git a/llvm/test/CodeGen/AArch64/avgfloor-u8.ll b/llvm/test/CodeGen/AArch64/avgfloor-u8.ll
new file mode 100644
index 0000000000000..669f6bbad14a3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/avgfloor-u8.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm64 -mcpu=apple-m1 | FileCheck %s
+
+; CHECK-LABEL: avg:
+; CHECK:       add
+; CHECK:       lsr
+; CHECK:       ret
+
+define zeroext i8 @avg(i8 noundef zeroext %a, i8 noundef zeroext %b) {
+entry:
+  %conv = zext i8 %a to i16
+  %conv1 = zext i8 %b to i16
+  %add = add nuw nsw i16 %conv1, %conv
+  %div3 = lshr i16 %add, 1
+  %conv2 = trunc nuw i16 %div3 to i8
+  ret i8 %conv2
+}