[llvm] e608e3f - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-07-11T10:12:32+01:00
New Revision: e608e3f023603c3687ed2da6f2e6408668ab28e6

URL: https://github.com/llvm/llvm-project/commit/e608e3f023603c3687ed2da6f2e6408668ab28e6
DIFF: https://github.com/llvm/llvm-project/commit/e608e3f023603c3687ed2da6f2e6408668ab28e6.diff

LOG: Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index f6f892a5ed994..79d309fed7f02 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -2018,7 +2018,7 @@ HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const {
     SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Val32);
     SmallVector<SDValue, 32> Mask;
     for (unsigned i = 0; i < 32; ++i)
-      Mask.push_back(DAG.getConstant(1u << i, dl, MVT::i32));
+      Mask.push_back(DAG.getConstant(1ull << i, dl, MVT::i32));
 
     SDValue MaskVec = DAG.getBuildVector(VecTy, dl, Mask);
     SDValue Anded = DAG.getNode(ISD::AND, dl, VecTy, Splat, MaskVec);