[llvm] [Hexagon] Add saturating scalar add for i32/i64 (PR #148132)

[via llvm-commits]

https://github.com/aankit-quic updated https://github.com/llvm/llvm-project/pull/148132

>From 22ddc33e8dfe3b57505c6f1e0034d7c19814e088 Mon Sep 17 00:00:00 2001
From: aankit-quic <aankit at quicinc.com>
Date: Fri, 11 Jul 2025 00:25:20 -0700
Subject: [PATCH] [Hexagon] Add Saturating add instructions

Generate the saturating add instructions for sadd.sat for scalar and
vector types

Co-authored-by: Jyotsna Verma <jverma at quicinc.com>
Change-Id: Ie768876b3c6c33aafcf725a0b688dfcb9278e62c
---
 .../Target/Hexagon/HexagonISelLowering.cpp    |  3 +++
 llvm/lib/Target/Hexagon/HexagonPatterns.td    |  8 +++++++
 llvm/test/CodeGen/Hexagon/addsat.ll           | 22 +++++++++++++++++++
 3 files changed, 33 insertions(+)
 create mode 100644 llvm/test/CodeGen/Hexagon/addsat.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 00925ed42fcd4..d123a06cc5d9e 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1687,6 +1687,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::SRL, VT, Custom);
   }
 
+  setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
+  setOperationAction(ISD::SADDSAT, MVT::i64, Legal);
+
   // Extending loads from (native) vectors of i8 into (native) vectors of i16
   // are legal.
   setLoadExtAction(ISD::EXTLOAD,  MVT::v2i16, MVT::v2i8, Legal);
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 2a991bafbf148..2337f185c7b36 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -1517,6 +1517,14 @@ def: Pat<(or  I32:$Rs, anyimm:$s10),   (A2_orir   I32:$Rs,  imm:$s10)>;
 def: Pat<(and I32:$Rs, anyimm:$s10),   (A2_andir  I32:$Rs,  imm:$s10)>;
 def: Pat<(sub anyimm:$s10, I32:$Rs),   (A2_subri  imm:$s10, I32:$Rs)>;
 
+class OpR_RR_pat_sat<InstHexagon MI, SDNode Op, ValueType ResType,
+                     PatFrag RxPred>
+  : Pat<(ResType (Op RxPred:$Rs, RxPred:$Rt)),
+        (MI RxPred:$Rs, RxPred:$Rt)>;
+
+def: OpR_RR_pat_sat<A2_addsat,  saddsat, i32, I32>;
+def: OpR_RR_pat_sat<A2_addpsat, saddsat, i64, I64>;
+
 def: OpR_RR_pat<A2_add,       Add,        i32,   I32>;
 def: OpR_RR_pat<A2_sub,       Sub,        i32,   I32>;
 def: OpR_RR_pat<A2_and,       And,        i32,   I32>;
diff --git a/llvm/test/CodeGen/Hexagon/addsat.ll b/llvm/test/CodeGen/Hexagon/addsat.ll
new file mode 100644
index 0000000000000..f958171ee3ae2
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/addsat.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Test for saturating add instructions.
+
+; CHECK-LABEL: test13
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},r{{[0-9]+}}):sat
+define i32 @test13(i32 %a0, i32 %a1) {
+entry:
+  %add = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 %a1)
+  ret i32 %add
+}
+
+; CHECK-LABEL: test14
+; CHECK: r{{[0-9]+}}:{{[0-9]+}} = add(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}}):sat
+define i64 @test14(i64 %a0, i64 %a1) {
+entry:
+  %add = call i64 @llvm.sadd.sat.i64(i64 %a0, i64 %a1)
+  ret i64 %add
+}
+
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare i64 @llvm.sadd.sat.i64(i64, i64)