[llvm] [RISCV] Align MCOperandPredicates with AsmParser (PR #146184)

[Fangrui Song via llvm-commits]

MaskRay wrote:

The changes that remove MCOp.isBareSymbolRef() uses look good, e.g. the change that replaces

```
def simm5 : RISCVSImmLeafOp<5> {
  let MCOperandPredicate = [{
    int64_t Imm;
    if (MCOp.evaluateAsConstantImm(Imm))
      return isInt<5>(Imm);
    return MCOp.isBareSymbolRef();
  }];
}
```

with

```
def simm5 : RISCVSImmLeafOp<5> {
  let MCOperandPredicate = [{
    int64_t Imm;
    if (!MCOp.evaluateAsConstantImm(Imm))
      return false;
    return isInt<5>(Imm);
  }];
}
```

We might want an API to extract the relocation specifier from a MCOperand, but it should not be called `SymbolRef` as `%specifier(sym_a-sym_b+cst)` should be allowed as well.


I just realized that this is closely tied to relocatin specifier design issue I filed in April: https://github.com/llvm/llvm-project/issues/135592 .
I'm not satisfied with how LLVM MC handles relocation specifier encoding.
Relocation specifier can be encoded by every sub-expression in the MCExpr tree, rather than the fixup itself (or the instruction, as in GNU Assembler).

```
MCBinaryExpr
  MCSymbolRef specifier
  MCSymbolRef

MCBinaryExpr
  MCSymbolRef
  MCSymbolRef specifier

RISCVMCExpr specifier
  MCSymbolRef

AArch64MCExpr specifier
  MCSymbolRef

// now XXXMCExpr have been unified to MCSpecifierExpr
```

It might be ideal to encode the MCExpr and relocation specifier as a pair, eliminating the need for MCSpecifierExpr to simply wrap a pointer, which would save memory.
However, MCOperand is size-sensitive, and we cannot include an additional integer as part of MCOperand.

We should consider the interplay of MCFixup and MCOperand, and how to encode relocation specifier. A change like this that excludes certain relocation specifiers from MCOperandPredicate, can be valuable in the future.


https://github.com/llvm/llvm-project/pull/146184