[llvm] [AMDGPU] Allocate AVRegClass last (PR #146606)

[Jeffrey Byrnes via llvm-commits]

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@@ -180,12 +188,22 @@ void RegAllocBase::cleanupFailedVReg(Register FailedReg, MCRegister PhysReg,
       for (MachineOperand &MO : MRI->reg_operands(*Aliases)) {
         if (MO.readsReg()) {
           MO.setIsUndef(true);
+          if (MO.getParent()->isCopy() && MO.isUse())
+            UndefCopies.push_back(MO.getParent());
           LIS->removeAllRegUnitsForPhysReg(MO.getReg());
         }
       }
     }
   }
 
+  // If we have produced an undef copy, convert to IMPLICIT_DEF.
+  for (MachineInstr *UndefCopy : UndefCopies) {
+    assert(UndefCopy->isCopy() && UndefCopy->getNumOperands() == 2);
+    const MCInstrDesc &Desc = TII->get(TargetOpcode::IMPLICIT_DEF);
+    UndefCopy->removeOperand(1);
+    UndefCopy->setDesc(Desc);
+  }
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jrbyrnes wrote:

Hey John --

That functionality is indirectly related to the AVGPR allocation order.

The change in allocation order resulted in some verifier failures (e.g. regalloc-failure-overlapping-insert-assert.mir). The change to allocation order has exposed a pre-existing issue which is being addressed by https://github.com/llvm/llvm-project/pull/147392 . I brought that PR into this one so that I wouldn't need to remove e.g.--verify-machineinstrs in those problematic tests.

The plan is to land the issue fix, then rebase this PR on top of trunk after it lands s.t. the only changes contained here will be the changes related to allocation order.

https://github.com/llvm/llvm-project/pull/146606