[llvm] [AMDGPU] Allocate AVRegClass last (PR #146606)

[via llvm-commits]

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@@ -180,12 +188,22 @@ void RegAllocBase::cleanupFailedVReg(Register FailedReg, MCRegister PhysReg,
       for (MachineOperand &MO : MRI->reg_operands(*Aliases)) {
         if (MO.readsReg()) {
           MO.setIsUndef(true);
+          if (MO.getParent()->isCopy() && MO.isUse())
+            UndefCopies.push_back(MO.getParent());
           LIS->removeAllRegUnitsForPhysReg(MO.getReg());
         }
       }
     }
   }
 
+  // If we have produced an undef copy, convert to IMPLICIT_DEF.
+  for (MachineInstr *UndefCopy : UndefCopies) {
+    assert(UndefCopy->isCopy() && UndefCopy->getNumOperands() == 2);
+    const MCInstrDesc &Desc = TII->get(TargetOpcode::IMPLICIT_DEF);
+    UndefCopy->removeOperand(1);
+    UndefCopy->setDesc(Desc);
+  }
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LU-JOHN wrote:

How is converting an undef copy to an IMPLICIT_DEF connected to setting register class priorities?  Just wondering why is it in this PR.

https://github.com/llvm/llvm-project/pull/146606