[llvm] [ISel/RISCV] Custom-lower vector [l]lround (PR #147713)

[Ramkumar Ramachandra via llvm-commits]

================
@@ -1,35 +1,28 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfh -target-abi=ilp32d \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfh -target-abi=lp64d \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d,+zvfhmin,+zvfbfmin -target-abi=lp64d \
----------------
artagnon wrote:

I don't think it's important either, as Zvfh will simply mark f16 as legal, and Zvfhmin is the interesting case.

https://github.com/llvm/llvm-project/pull/147713