[llvm] [AArch64] Keep floating-point conversion in SIMD (PR #147707)

[David Sherwood via llvm-commits]

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@@ -6632,6 +6644,38 @@ def : Pat<(f64 (sint_to_fp (i64 (vector_extract (v2i64 FPR128:$Rn), (i64 0))))),
 def : Pat<(f64 (uint_to_fp (i64 (vector_extract (v2i64 FPR128:$Rn), (i64 0))))),
           (UCVTFv1i64 (i64 (EXTRACT_SUBREG (v2i64 FPR128:$Rn), dsub)))>;
 
+// float -> int conversion followed by a store should use the value in the first
+// lane to avoid expensive fpr -> gpr transfers.
+let AddedComplexity = 19 in {
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david-arm wrote:

Is this essentially competing with VecStoreLane0Pat, which also has AddedComplexity=19? Does the value need to be higher?

https://github.com/llvm/llvm-project/pull/147707