[llvm] [RISCV] Prefer preindexed addressing mode when XTheadMemIdx exists (PR #147921)

[Pengcheng Wang via llvm-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/147921

The experimental result shows that we can generate more XTheadMemIdx
instructions when using preindexed addressing mode.

| -lsr-preferred-addressing-mode | Num   |
|--------------------------------|-------|
| none                           | 47308 |
| preindexed                     | 54125 |
| postindexed                    | 50255 |


>From 43ca176fc9ee17fb141221afb8029e85f8d3c58e Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Thu, 10 Jul 2025 17:01:49 +0800
Subject: [PATCH] [RISCV] Prefer preindexed addressing mode when XTheadMemIdx
 exists

The experimental result shows that we can generate more XTheadMemIdx
instructions when using preindexed addressing mode.

| -lsr-preferred-addressing-mode | Num   |
|--------------------------------|-------|
| none                           | 47308 |
| preindexed                     | 54125 |
| postindexed                    | 50255 |
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 67a51c12b508e..c07472a55c731 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2709,6 +2709,9 @@ RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
   if (ST->hasVendorXCVmem() && !ST->is64Bit())
     return TTI::AMK_PostIndexed;
 
+  if (ST->hasVendorXTHeadMemIdx())
+    return TTI::AMK_PreIndexed;
+
   return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
 }