[llvm] [X86] combineStore - remove rangedata when converting 64-bit copies to f64 load/store (PR #147904)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 10 00:16:57 PDT 2025
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/147904
We're changing from i64 to f64 - we can't retain any range metadata
Fixes #147781
>From 263cb6ecc701b23fcc47e1813d512de20142e094 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Thu, 10 Jul 2025 08:15:47 +0100
Subject: [PATCH] [X86] combineStore - remove rangedata when converting 64-bit
copies to f64 load/store
We're changing from i64 to f64 - we can't retain any range metadata
Fixes #147781
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++++
llvm/test/CodeGen/X86/pr147781.ll | 19 +++++++++++++++++++
2 files changed, 23 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/pr147781.ll
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 347ba1262b66b..1ad1b47a94d28 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53574,6 +53574,10 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
SDLoc LdDL(Ld);
SDLoc StDL(N);
+
+ // Remove any range metadata as we're converting to f64 load/store.
+ Ld->getMemOperand()->clearRanges();
+
// Lower to a single movq load/store pair.
SDValue NewLd = DAG.getLoad(MVT::f64, LdDL, Ld->getChain(),
Ld->getBasePtr(), Ld->getMemOperand());
diff --git a/llvm/test/CodeGen/X86/pr147781.ll b/llvm/test/CodeGen/X86/pr147781.ll
new file mode 100644
index 0000000000000..9f65fd5984e7b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr147781.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-pc-windows-gnu -verify-machineinstrs | FileCheck %s
+
+; Ensure i64 !range data is stripped when converting to f64 load/store.
+define void @test(ptr %p, ptr %p2) #0 {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT: movsd %xmm0, (%eax)
+; CHECK-NEXT: retl
+ %val = load i64, ptr %p, align 8, !range !0
+ store i64 %val, ptr %p2, align 8
+ ret void
+}
+
+attributes #0 = { "target-cpu"="pentium4" }
+!0 = !{i64 1, i64 0}
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