[llvm] b57df56 - [RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 9 23:15:26 PDT 2025
Author: Pengcheng Wang
Date: 2025-07-10T14:15:22+08:00
New Revision: b57df56b48145f0985c5cab4e4f282e512c89546
URL: https://github.com/llvm/llvm-project/commit/b57df56b48145f0985c5cab4e4f282e512c89546
DIFF: https://github.com/llvm/llvm-project/commit/b57df56b48145f0985c5cab4e4f282e512c89546.diff
LOG: [RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
There will be more schedule definitions for vendor extentions and
we need to add these `UnsupportedSchedXXX` to exsiting models every
time we add new schedule definitions.
The fact is that each vendor will barely implement other vendors'
extensions, so we can package these definitions into one.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVSchedAndes45.td
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
llvm/lib/Target/RISCV/RISCVSchedule.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index bd480aacc539e..da0ceee0c0840 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -330,14 +330,10 @@ def : ReadAdvance<ReadCSR, 0>;
defm : UnsupportedSchedQ;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedV;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
index 6ad5a008f11ab..3786754527336 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
@@ -497,9 +497,5 @@ defm : UnsupportedSchedV;
defm : UnsupportedSchedZfaWithQ;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index 4117d7a9f1d58..c0d6ef72a839e 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -273,10 +273,6 @@ defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index b24801f6ecefe..7d072b56e582c 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -262,10 +262,6 @@ defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index cb6619b198374..c4ae4d7d829be 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -1238,9 +1238,5 @@ defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
index 7dc007f986398..9058514560c7d 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
@@ -358,9 +358,5 @@ defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index a608c23c11a02..c989e1ceb4b0e 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -1494,9 +1494,5 @@ defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index 26439df3199ce..b0e1c7056c34d 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -1183,9 +1183,5 @@ defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfaWithQ;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 85429ad1806c9..05388f2d13113 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -345,15 +345,11 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
// Unsupported extensions
defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
index 727b8d2152c22..56fd45d7c9721 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -116,10 +116,6 @@ defm : UnsupportedSchedZbs;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
index 3949eee4a96e8..9165697d0b493 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
@@ -182,11 +182,6 @@ multiclass SCR_Other {
multiclass SCR_Unsupported :
UnsupportedSchedSFB,
UnsupportedSchedV,
- UnsupportedSchedXsfvcp,
- UnsupportedSchedXSfvfnrclipxfqf,
- UnsupportedSchedXSfvfwmaccqqq,
- UnsupportedSchedXSfvqmaccdod,
- UnsupportedSchedXSfvqmaccqoq,
UnsupportedSchedZabha,
UnsupportedSchedZba,
UnsupportedSchedZbb,
@@ -195,7 +190,8 @@ multiclass SCR_Unsupported :
UnsupportedSchedZbkb,
UnsupportedSchedZbkx,
UnsupportedSchedZfa,
- UnsupportedSchedZvk;
+ UnsupportedSchedZvk,
+ UnsupportedSchedXsf;
multiclass SCR3_Unsupported :
SCR_Unsupported,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
index f3aae307eb717..3ebc77d277269 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
@@ -244,15 +244,11 @@ multiclass SCR7_Unsupported {
defm : UnsupportedSchedQ;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedV;
- defm : UnsupportedSchedXsfvcp;
- defm : UnsupportedSchedXSfvfnrclipxfqf;
- defm : UnsupportedSchedXSfvfwmaccqqq;
- defm : UnsupportedSchedXSfvqmaccdod;
- defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedZvk;
+ defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 2a2fc854ea296..da89e158f9839 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -320,11 +320,6 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
// Unsupported extensions
defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
@@ -332,4 +327,5 @@ defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
index 5aad7f5b9e65d..989ebbd32733f 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
@@ -312,10 +312,6 @@ defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
-defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedXSfvfnrclipxfqf;
-defm : UnsupportedSchedXSfvfwmaccqqq;
-defm : UnsupportedSchedXSfvqmaccdod;
-defm : UnsupportedSchedXSfvqmaccqoq;
defm : UnsupportedSchedZvk;
+defm : UnsupportedSchedXsf;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
index 4d49ad4d6b317..9ab9636a79cbe 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -519,3 +519,12 @@ include "RISCVScheduleZb.td"
include "RISCVScheduleV.td"
include "RISCVScheduleXSf.td"
include "RISCVScheduleZvk.td"
+
+// Vendor Extensions
+multiclass UnsupportedSchedXsf {
+ defm : UnsupportedSchedXsfvcp;
+ defm : UnsupportedSchedXSfvfnrclipxfqf;
+ defm : UnsupportedSchedXSfvfwmaccqqq;
+ defm : UnsupportedSchedXSfvqmaccdod;
+ defm : UnsupportedSchedXSfvqmaccqoq;
+}
More information about the llvm-commits
mailing list