[llvm] [AMDGPU] Generate waterfall for calls with SGPR(inreg) argument (PR #146997)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 9 19:54:22 PDT 2025
================
@@ -1128,6 +1166,45 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
}
}
+void SIFixSGPRCopies::lowerPysicalSGPRInsts(MachineFunction &MF) {
+ for (auto &Entry : WaterFalls) {
+ MachineInstr *MI = Entry.first;
+ struct V2PysSCopyInfo Info = Entry.second;
+ if (Info.MOs.size() == 0 || Info.SGPRs.size() != Info.MOs.size())
+ continue;
+
+ if (MI->getOpcode() == AMDGPU::SI_CALL_ISEL) {
+ // Move everything between ADJCALLSTACKUP and ADJCALLSTACKDOWN and
+ // following copies, we also need to move copies from and to physical
+ // registers into the loop block.
+ unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
+ unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
+
+ // Also move the copies to physical registers into the loop block
+ MachineBasicBlock &MBB = *MI->getParent();
+ MachineBasicBlock::iterator Start(MI);
+ while (Start->getOpcode() != FrameSetupOpcode)
+ --Start;
+ MachineBasicBlock::iterator End(MI);
+ while (End->getOpcode() != FrameDestroyOpcode)
+ ++End;
+
+ // Also include following copies of the return value
+ ++End;
+ while (End != MBB.end() && End->isCopy() && End->getOperand(1).isReg() &&
+ MI->definesRegister(End->getOperand(1).getReg(), TRI))
+ ++End;
+
+ llvm::loadMBUFScalarOperandsFromVGPR(*TII, *MI, Info.MOs, MDT, Start, End,
+ Info.SGPRs);
+ }
+ }
+ // Avoid some O0 tests where no use of COPY to SGPR
+ if (!WaterFalls.empty())
+ for (auto &Entry : V2PhySCopies)
+ Entry->eraseFromParent();
----------------
Shoreshen wrote:
Hi @jmmartinez , there are some tests will fail due to remove of it...
One of the example is llvm-project/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
The test is expected to fail due to a VGPR to SGPR copy without any use.
https://github.com/llvm/llvm-project/pull/146997
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