[llvm] [RISCV][Docs] Add bfloat types to RISCVVectorExtension.rst. NFC (PR #147867)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 9 18:09:49 PDT 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/147867
None
>From 927078918c14295713b3443fc387edd3b8455556 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 9 Jul 2025 18:08:49 -0700
Subject: [PATCH] [RISCV][Docs] Add bfloat types to RISCVVectorExtension.rst.
NFC
---
llvm/docs/RISCV/RISCVVectorExtension.rst | 36 +++++++++++++-----------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/llvm/docs/RISCV/RISCVVectorExtension.rst b/llvm/docs/RISCV/RISCVVectorExtension.rst
index cfe9abfbdfcdb..525b986f98df6 100644
--- a/llvm/docs/RISCV/RISCVVectorExtension.rst
+++ b/llvm/docs/RISCV/RISCVVectorExtension.rst
@@ -19,23 +19,25 @@ On RISC-V ``n`` and ``ty`` control LMUL and SEW respectively.
LLVM only supports ELEN=32 or ELEN=64, so ``vscale`` is defined as VLEN/64 (see ``RISCV::RVVBitsPerBlock``).
Note this means that VLEN must be at least 64, so VLEN=32 isn't currently supported.
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| | LMUL=⅛ | LMUL=¼ | LMUL=½ | LMUL=1 | LMUL=2 | LMUL=4 | LMUL=8 |
-+===================+===============+================+==================+===================+===================+===================+===================+
-| i64 (ELEN=64) | N/A | N/A | N/A | <v x 1 x i64> | <v x 2 x i64> | <v x 4 x i64> | <v x 8 x i64> |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| i32 | N/A | N/A | <v x 1 x i32> | <v x 2 x i32> | <v x 4 x i32> | <v x 8 x i32> | <v x 16 x i32> |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| i16 | N/A | <v x 1 x i16> | <v x 2 x i16> | <v x 4 x i16> | <v x 8 x i16> | <v x 16 x i16> | <v x 32 x i16> |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| i8 | <v x 1 x i8> | <v x 2 x i8> | <v x 4 x i8> | <v x 8 x i8> | <v x 16 x i8> | <v x 32 x i8> | <v x 64 x i8> |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| double (ELEN=64) | N/A | N/A | N/A | <v x 1 x double> | <v x 2 x double> | <v x 4 x double> | <v x 8 x double> |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| float | N/A | N/A | <v x 1 x float> | <v x 2 x float> | <v x 4 x float> | <v x 8 x float> | <v x 16 x float> |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| half | N/A | <v x 1 x half> | <v x 2 x half> | <v x 4 x half> | <v x 8 x half> | <v x 16 x half> | <v x 32 x half> |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| | LMUL=⅛ | LMUL=¼ | LMUL=½ | LMUL=1 | LMUL=2 | LMUL=4 | LMUL=8 |
++===================+===============+==================+==================+===================+===================+===================+===================+
+| i64 (ELEN=64) | N/A | N/A | N/A | <v x 1 x i64> | <v x 2 x i64> | <v x 4 x i64> | <v x 8 x i64> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| i32 | N/A | N/A | <v x 1 x i32> | <v x 2 x i32> | <v x 4 x i32> | <v x 8 x i32> | <v x 16 x i32> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| i16 | N/A | <v x 1 x i16> | <v x 2 x i16> | <v x 4 x i16> | <v x 8 x i16> | <v x 16 x i16> | <v x 32 x i16> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| i8 | <v x 1 x i8> | <v x 2 x i8> | <v x 4 x i8> | <v x 8 x i8> | <v x 16 x i8> | <v x 32 x i8> | <v x 64 x i8> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| double (ELEN=64) | N/A | N/A | N/A | <v x 1 x double> | <v x 2 x double> | <v x 4 x double> | <v x 8 x double> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| float | N/A | N/A | <v x 1 x float> | <v x 2 x float> | <v x 4 x float> | <v x 8 x float> | <v x 16 x float> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| half | N/A | <v x 1 x half> | <v x 2 x half> | <v x 4 x half> | <v x 8 x half> | <v x 16 x half> | <v x 32 x half> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| bfloat | N/A | <v x 1 x bfloat> | <v x 2 x bfloat> | <v x 4 x bfloat> | <v x 8 x bfloat> | <v x 16 x bfloat> | <v x 32 x bfloat> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
(Read ``<v x k x ty>`` as ``<vscale x k x ty>``)
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