[llvm] [SelectionDAG] fold (not (sub Y, X)) -> (add X, ~Y) (PR #147825)
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Wed Jul 9 15:04:38 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/147825
>From a1277e58283c382c6e16e9e827244a890242abb0 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Wed, 9 Jul 2025 16:48:35 -0400
Subject: [PATCH] [SelectionDAG] fold (not (sub Y, X)) -> (add X, ~Y)
This replaces (not (neg x)) -> (add X, -1) because that is covered by this.
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 17 ++++++++++-------
llvm/test/CodeGen/PowerPC/setcc-to-sub.ll | 10 +++++-----
llvm/test/CodeGen/PowerPC/testComparesigeuc.ll | 6 +++---
llvm/test/CodeGen/PowerPC/testComparesigeui.ll | 6 +++---
llvm/test/CodeGen/PowerPC/testComparesigeus.ll | 6 +++---
llvm/test/CodeGen/PowerPC/testComparesileuc.ll | 8 ++++----
llvm/test/CodeGen/PowerPC/testComparesileui.ll | 8 ++++----
llvm/test/CodeGen/PowerPC/testComparesileus.ll | 8 ++++----
llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll | 6 +++---
llvm/test/CodeGen/PowerPC/testComparesllgeui.ll | 6 +++---
llvm/test/CodeGen/PowerPC/testComparesllgeus.ll | 6 +++---
llvm/test/CodeGen/PowerPC/testComparesllleuc.ll | 8 ++++----
llvm/test/CodeGen/PowerPC/testComparesllleui.ll | 8 ++++----
llvm/test/CodeGen/PowerPC/testComparesllleus.ll | 8 ++++----
llvm/test/CodeGen/X86/pr31045.ll | 8 ++++----
15 files changed, 61 insertions(+), 58 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9ffdda28f7899..401319c3c7130 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9979,13 +9979,16 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
}
}
- // fold (not (neg x)) -> (add X, -1)
- // FIXME: This can be generalized to (not (sub Y, X)) -> (add X, ~Y) if
- // Y is a constant or the subtract has a single use.
- if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB &&
- isNullConstant(N0.getOperand(0))) {
- return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1),
- DAG.getAllOnesConstant(DL, VT));
+ // fold (not (sub Y, X)) -> (add X, ~Y) if subtract is a single use
+ // or Y is a constant.
+ if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
+ if (isa<ConstantSDNode>(N00) || N0.hasOneUse()) {
+ SDValue NotY =
+ DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00
+ AddToWorklist(NotY.getNode());
+ return DAG.getNode(ISD::ADD, DL, VT, N01, NotY);
+ }
}
// fold (not (add X, -1)) -> (neg X)
diff --git a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
index 20dcb8ccf4908..d2ca198d8fcda 100644
--- a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
@@ -31,12 +31,12 @@ entry:
define zeroext i1 @test2(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: lwz 4, 0(4)
-; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
+; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: not 3, 3
+; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
+; CHECK-NEXT: not 4, 4
+; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -76,8 +76,8 @@ define zeroext i1 @test4(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
; CHECK-NEXT: lwz 4, 0(4)
; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
-; CHECK-NEXT: sub 3, 3, 4
; CHECK-NEXT: not 3, 3
+; CHECK-NEXT: add 3, 4, 3
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
index 37e589711f2db..6839578d45644 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -12,8 +12,8 @@
define dso_local signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -65,9 +65,9 @@ entry:
define dso_local void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
index fc951124cf2a3..2d28d2ff94641 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -12,8 +12,8 @@
define dso_local signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -64,9 +64,9 @@ entry:
define dso_local void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
index 522de14e4798a..e78381d937544 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
@@ -12,8 +12,8 @@
define dso_local signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -64,9 +64,9 @@ entry:
define dso_local void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
index 1b6d1ae17c9b0..17a332d647b91 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
@@ -12,8 +12,8 @@
define dso_local signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -67,9 +67,9 @@ entry:
define dso_local void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileui.ll b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
index 4c1efde742db9..e121bdfbbcc42 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesileui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
@@ -12,8 +12,8 @@
define dso_local signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -67,9 +67,9 @@ entry:
define dso_local void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileus.ll b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
index 31952081f3db9..14e2a87a95292 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesileus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
@@ -12,8 +12,8 @@
define dso_local signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -67,9 +67,9 @@ entry:
define dso_local void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
index 14519472ad01d..464b92e5c9169 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -12,8 +12,8 @@
define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgeuc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -64,9 +64,9 @@ entry:
define dso_local void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgeuc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
index 6161109dbf923..31dde3c3f300e 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -12,8 +12,8 @@
define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgeui:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -64,9 +64,9 @@ entry:
define dso_local void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgeui_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
index a22def4beaf70..0d46fb9c6bf69 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -12,8 +12,8 @@
define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgeus:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -64,9 +64,9 @@ entry:
define dso_local void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgeus_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: addis r4, r2, glob at toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
index cfaa6e8fe1d83..a5d74ad1201db 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
@@ -12,8 +12,8 @@
define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llleuc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -67,9 +67,9 @@ entry:
define dso_local void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llleuc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
index e438797cde772..1be2497b77193 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
@@ -12,8 +12,8 @@
define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llleui:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -67,9 +67,9 @@ entry:
define dso_local void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llleui_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
index 53b9b8a16d503..e84e3fbb4707e 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
@@ -12,8 +12,8 @@
define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llleus:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
@@ -67,9 +67,9 @@ entry:
define dso_local void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llleus_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r4, r4
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/X86/pr31045.ll b/llvm/test/CodeGen/X86/pr31045.ll
index 4aa73d79d8cfc..a873fc6fd4959 100644
--- a/llvm/test/CodeGen/X86/pr31045.ll
+++ b/llvm/test/CodeGen/X86/pr31045.ll
@@ -21,11 +21,11 @@ define void @_Z1av() local_unnamed_addr #0 {
; CHECK-NEXT: movl struct_obj_3+8(%rip), %eax
; CHECK-NEXT: movzbl var_46(%rip), %ecx
; CHECK-NEXT: movzbl var_49(%rip), %edx
-; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: addl %eax, %eax
-; CHECK-NEXT: subl %ecx, %eax
-; CHECK-NEXT: subl %edx, %eax
+; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: notl %eax
+; CHECK-NEXT: addl %eax, %eax
+; CHECK-NEXT: orl $253, %eax
+; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movw %ax, struct_obj_12+5(%rip)
; CHECK-NEXT: movb $0, var_163(%rip)
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