[llvm] [RISCV] Use Selection::haveNoCommonBitsSet in RISCVDAGToDAGISel::orDisjoint. (PR #147838)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/147838.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+2-3) 
- (modified) llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll (+5-8) 
- (modified) llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll (+2-4) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index ae99b620cf436..11e4b2d8e0899 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3464,11 +3464,10 @@ bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
 }
 
 bool RISCVDAGToDAGISel::orDisjoint(const SDNode *N) const {
+  assert(N->getOpcode() == ISD::OR || N->getOpcode() == RISCVISD::OR_VL);
   if (N->getFlags().hasDisjoint())
     return true;
-  KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
-  KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
-  return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+  return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
 }
 
 bool RISCVDAGToDAGISel::selectImm64IfCheaper(int64_t Imm, int64_t OrigImm,
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
index 0d6dba61b9a14..1736074ab1868 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
@@ -205,8 +205,7 @@ define i32 @inverted_masked_merge_i32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32ZBB-ZBKB:       # %bb.0:
 ; RV32ZBB-ZBKB-NEXT:    and a1, a0, a1
 ; RV32ZBB-ZBKB-NEXT:    andn a0, a2, a0
-; RV32ZBB-ZBKB-NEXT:    or a0, a1, a0
-; RV32ZBB-ZBKB-NEXT:    not a0, a0
+; RV32ZBB-ZBKB-NEXT:    xnor a0, a1, a0
 ; RV32ZBB-ZBKB-NEXT:    ret
   %a = and i32 %x, %y
   %notx = xor i32 %x, -1
@@ -231,14 +230,12 @@ define i64 @inverted_masked_merge_i64(i64 %x, i64 %y, i64 %z) nounwind {
 ;
 ; RV32ZBB-ZBKB-LABEL: inverted_masked_merge_i64:
 ; RV32ZBB-ZBKB:       # %bb.0:
-; RV32ZBB-ZBKB-NEXT:    and a2, a0, a2
 ; RV32ZBB-ZBKB-NEXT:    and a3, a1, a3
-; RV32ZBB-ZBKB-NEXT:    andn a0, a4, a0
+; RV32ZBB-ZBKB-NEXT:    and a2, a0, a2
 ; RV32ZBB-ZBKB-NEXT:    andn a1, a5, a1
-; RV32ZBB-ZBKB-NEXT:    or a1, a3, a1
-; RV32ZBB-ZBKB-NEXT:    or a0, a2, a0
-; RV32ZBB-ZBKB-NEXT:    not a0, a0
-; RV32ZBB-ZBKB-NEXT:    not a1, a1
+; RV32ZBB-ZBKB-NEXT:    andn a0, a4, a0
+; RV32ZBB-ZBKB-NEXT:    xnor a0, a2, a0
+; RV32ZBB-ZBKB-NEXT:    xnor a1, a3, a1
 ; RV32ZBB-ZBKB-NEXT:    ret
   %a = and i64 %x, %y
   %notx = xor i64 %x, -1
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
index 36e5958fcba5b..12fc98c7edab8 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
@@ -186,8 +186,7 @@ define signext i32 @inverted_masked_merge_i32(i32 signext %x, i32 signext %y, i3
 ; RV64ZBB-ZBKB:       # %bb.0:
 ; RV64ZBB-ZBKB-NEXT:    and a1, a0, a1
 ; RV64ZBB-ZBKB-NEXT:    andn a0, a2, a0
-; RV64ZBB-ZBKB-NEXT:    or a0, a1, a0
-; RV64ZBB-ZBKB-NEXT:    not a0, a0
+; RV64ZBB-ZBKB-NEXT:    xnor a0, a1, a0
 ; RV64ZBB-ZBKB-NEXT:    ret
   %a = and i32 %x, %y
   %notx = xor i32 %x, -1
@@ -210,8 +209,7 @@ define i64 @inverted_masked_merge_i64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV64ZBB-ZBKB:       # %bb.0:
 ; RV64ZBB-ZBKB-NEXT:    and a1, a0, a1
 ; RV64ZBB-ZBKB-NEXT:    andn a0, a2, a0
-; RV64ZBB-ZBKB-NEXT:    or a0, a1, a0
-; RV64ZBB-ZBKB-NEXT:    not a0, a0
+; RV64ZBB-ZBKB-NEXT:    xnor a0, a1, a0
 ; RV64ZBB-ZBKB-NEXT:    ret
   %a = and i64 %x, %y
   %notx = xor i64 %x, -1

``````````

</details>


https://github.com/llvm/llvm-project/pull/147838