[llvm] [AMDGPU] Support merging 16-bit TBUFFER load/store instruction (PR #145078)

[Jay Foad via llvm-commits]

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@@ -1040,32 +1048,55 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
   if (CI.Offset == Paired.Offset)
     return false;
 
+  unsigned EltSize = CI.EltSize;
+
   // This won't be valid if the offset isn't aligned.
-  if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0))
+  if ((CI.Offset % EltSize != 0) || (Paired.Offset % EltSize != 0))
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jayfoad wrote:

Why change this?

https://github.com/llvm/llvm-project/pull/145078