[llvm] [AMDGPU] Support function attribute to override postRA scheduling direction (PR #147708)

[Harrison Hao via llvm-commits]

https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/147708

>From ea360350ce6320fcb70b2ce440468aba0767bb79 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 9 Jul 2025 17:46:23 +0800
Subject: [PATCH 1/2] [AMDGPU] Support function attribute to override postRA
 scheduling direction

---
 llvm/include/llvm/CodeGen/MachineScheduler.h   |  1 +
 llvm/lib/CodeGen/MachineScheduler.cpp          |  2 +-
 llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 17 +++++++++++++++++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index e7a7091acee64..1635eae758590 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -116,6 +116,7 @@ enum Direction {
 } // namespace MISched
 
 LLVM_ABI extern cl::opt<MISched::Direction> PreRADirection;
+LLVM_ABI extern cl::opt<MISched::Direction> PostRADirection;
 LLVM_ABI extern cl::opt<bool> VerifyScheduling;
 #ifndef NDEBUG
 extern cl::opt<bool> ViewMISchedDAGs;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 76cba2949af60..72e1fce07f33e 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -190,7 +190,7 @@ cl::opt<MISched::Direction> PreRADirection(
         clEnumValN(MISched::Bidirectional, "bidirectional",
                    "Force bidirectional pre reg-alloc list scheduling")));
 
-static cl::opt<MISched::Direction> PostRADirection(
+cl::opt<MISched::Direction> PostRADirection(
     "misched-postra-direction", cl::Hidden,
     cl::desc("Post reg-alloc list scheduling direction"),
     cl::init(MISched::Unspecified),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index c3536113e9bef..4c46e703b4604 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1144,6 +1144,23 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
 
 ScheduleDAGInstrs *
 GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
+  Attribute PostRADirectionAttr =
+      C->MF->getFunction().getFnAttribute("misched-postra-direction");
+
+  if (PostRADirectionAttr.isValid()) {
+    StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString();
+    if (PostRADirectionStr == "topdown")
+      PostRADirection = MISched::TopDown;
+    else if (PostRADirectionStr == "bottomup")
+      PostRADirection = MISched::BottomUp;
+    else if (PostRADirectionStr == "bidirectional")
+      PostRADirection = MISched::Bidirectional;
+    else
+      report_fatal_error(
+          Twine("invalid value for 'misched-postra-direction' attribute: ") +
+          PostRADirectionStr);
+  }
+
   ScheduleDAGMI *DAG =
       new GCNPostScheduleDAGMILive(C, std::make_unique<PostGenericScheduler>(C),
                                    /*RemoveKillFlags=*/true);

>From 4bcd9a6d13fc8b97b31e128384ae6d93533b2b4f Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 9 Jul 2025 14:50:38 +0000
Subject: [PATCH 2/2] Use reportFatalUsageError.

---
 llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 4c46e703b4604..28d8b08cf32a5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1156,7 +1156,7 @@ GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
     else if (PostRADirectionStr == "bidirectional")
       PostRADirection = MISched::Bidirectional;
     else
-      report_fatal_error(
+      reportFatalUsageError(
           Twine("invalid value for 'misched-postra-direction' attribute: ") +
           PostRADirectionStr);
   }