[llvm] [RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (PR #144703)

Alex Bradbury via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 9 05:55:28 PDT 2025


asb wrote:

> I'm about to push changes to this patch to limit it to just the LWU change. Looking at the diffs between doing it at isel and this way, there are some cases where at first glance I would have thought would have been handled - I'll pick through a couple just to check there's nothing surprising going on.

I looked into this some more, and an issue with my SDag patch posted above is that if you have a load where the result is used by another instruction, but the chain is also used by a store, then that use of the chain causes hasAllNbitUsers to return false. So adding this fixes that:
```
@@ -3548,6 +3549,9 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
     // Users of this node should have already been instruction selected
     if (!User->isMachineOpcode())
       return false;
+    // Skip uses of a chain result.
+    if (Node->getValueType(Use.getResNo()) == MVT::Other)
+      continue;

     // TODO: Add more opcodes?
     switch (User->getMachineOpcode()) {
```

This bumps us up to ~8400 changed instructions across llvm-test-suite so still limited vs the RISCVOptWInstrs approach.

I think investigating doing this at ISel time as well may be worthwhile in the fullness of time, but for now doing it at RISCVOptWInstrs seems the simplest path forwards that solves the immediate problem.

https://github.com/llvm/llvm-project/pull/144703


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