[llvm] b02920f - [RISCV] Don't increase vslide or splat vl if +vl-dependent-latency is present (#147089)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 9 01:25:25 PDT 2025
Author: Luke Lau
Date: 2025-07-09T16:25:22+08:00
New Revision: b02920f36970264d7cbddbe2d432c2d3a8361f1a
URL: https://github.com/llvm/llvm-project/commit/b02920f36970264d7cbddbe2d432c2d3a8361f1a
DIFF: https://github.com/llvm/llvm-project/commit/b02920f36970264d7cbddbe2d432c2d3a8361f1a.diff
LOG: [RISCV] Don't increase vslide or splat vl if +vl-dependent-latency is present (#147089)
If the subtarget's latency is dependent on vl, then we shouldn't try to
fold away vsetvli toggles if it means increasing vl.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index dd002473a06e2..90e1c47a71c89 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -421,10 +421,12 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
// * We can't modify SEW here since the slide amount is in units of SEW.
// * VL=1 is special only because we have existing support for zero vs
// non-zero VL. We could generalize this if we had a VL > C predicate.
- // * The LMUL1 restriction is for machines whose latency may depend on VL.
+ // * The LMUL1 restriction is for machines whose latency may depend on LMUL.
// * As above, this is only legal for tail "undefined" not "agnostic".
+ // * We avoid increasing vl if the subtarget has +vl-dependent-latency
if (RISCVInstrInfo::isVSlideInstr(MI) && VLOp.isImm() &&
- VLOp.getImm() == 1 && hasUndefinedPassthru(MI)) {
+ VLOp.getImm() == 1 && hasUndefinedPassthru(MI) &&
+ !ST->hasVLDependentLatency()) {
Res.VLAny = false;
Res.VLZeroness = true;
Res.LMUL = DemandedFields::LMULLessThanOrEqualToM1;
@@ -438,7 +440,8 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
// careful to not increase the number of active vector registers (unlike for
// vmv.s.x.)
if (RISCVInstrInfo::isScalarSplatInstr(MI) && VLOp.isImm() &&
- VLOp.getImm() == 1 && hasUndefinedPassthru(MI)) {
+ VLOp.getImm() == 1 && hasUndefinedPassthru(MI) &&
+ !ST->hasVLDependentLatency()) {
Res.LMUL = DemandedFields::LMULLessThanOrEqualToM1;
Res.SEWLMULRatio = false;
Res.VLAny = false;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index 67a09b071c1a8..acc2a97dd5d1f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -13,23 +13,43 @@
declare <vscale x 1 x i1> @llvm.vector.splice.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>, i32)
define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) #0 {
-; CHECK-LABEL: splice_nxv1i1_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v10, 1
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1i1_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1i1_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x i1> @llvm.vector.splice.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i32 -1)
ret <vscale x 1 x i1> %res
}
@@ -79,23 +99,43 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
declare <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)
define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 {
-; CHECK-LABEL: splice_nxv2i1_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v10, 1
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv2i1_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2i1_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 -1)
ret <vscale x 2 x i1> %res
}
@@ -145,23 +185,43 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
declare <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, i32)
define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 {
-; CHECK-LABEL: splice_nxv4i1_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v10, 1
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv4i1_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: srli a0, a0, 1
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv4i1_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: srli a0, a0, 1
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 -1)
ret <vscale x 4 x i1> %res
}
@@ -211,22 +271,41 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
declare <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, i32)
define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 {
-; CHECK-LABEL: splice_nxv8i1_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v10, 1
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv8i1_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv8i1_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 -1)
ret <vscale x 8 x i1> %res
}
@@ -274,23 +353,43 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
declare <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32)
define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
-; CHECK-LABEL: splice_nxv16i1_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v12, 1
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv16i1_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: slli a0, a0, 1
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v12, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv16i1_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: slli a0, a0, 1
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v12, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: ret
%res = call <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 -1)
ret <vscale x 16 x i1> %res
}
@@ -340,23 +439,43 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
declare <vscale x 32 x i1> @llvm.vector.splice.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, i32)
define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b) #0 {
-; CHECK-LABEL: splice_nxv32i1_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v16, 1
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv32i1_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmv.v.i v12, 0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmerge.vim v16, v12, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: slli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v16, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv32i1_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmv.v.i v12, 0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmerge.vim v16, v12, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: slli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, m4, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v16, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.vector.splice.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, i32 -1)
ret <vscale x 32 x i1> %res
}
@@ -406,23 +525,43 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
declare <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, i32)
define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) #0 {
-; CHECK-LABEL: splice_nxv64i1_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v24, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v16, 1
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv64i1_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmv.v.i v24, 0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
+; NOVLDEP-NEXT: slli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v16, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv64i1_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmv.v.i v24, 0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
+; VLDEP-NEXT: slli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, m8, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v16, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 -1)
ret <vscale x 64 x i1> %res
}
@@ -480,15 +619,26 @@ define <vscale x 1 x i8> @splice_nxv1i8_offset_zero(<vscale x 1 x i8> %a, <vscal
}
define <vscale x 1 x i8> @splice_nxv1i8_offset_negone(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
-; CHECK-LABEL: splice_nxv1i8_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1i8_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1i8_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -1)
ret <vscale x 1 x i8> %res
}
@@ -554,15 +704,26 @@ define <vscale x 2 x i8> @splice_nxv2i8_offset_zero(<vscale x 2 x i8> %a, <vscal
}
define <vscale x 2 x i8> @splice_nxv2i8_offset_negone(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
-; CHECK-LABEL: splice_nxv2i8_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv2i8_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2i8_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -1)
ret <vscale x 2 x i8> %res
}
@@ -628,15 +789,26 @@ define <vscale x 4 x i8> @splice_nxv4i8_offset_zero(<vscale x 4 x i8> %a, <vscal
}
define <vscale x 4 x i8> @splice_nxv4i8_offset_negone(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
-; CHECK-LABEL: splice_nxv4i8_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv4i8_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 1
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv4i8_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 1
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -1)
ret <vscale x 4 x i8> %res
}
@@ -702,14 +874,24 @@ define <vscale x 8 x i8> @splice_nxv8i8_offset_zero(<vscale x 8 x i8> %a, <vscal
}
define <vscale x 8 x i8> @splice_nxv8i8_offset_negone(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
-; CHECK-LABEL: splice_nxv8i8_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv8i8_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv8i8_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -1)
ret <vscale x 8 x i8> %res
}
@@ -1036,15 +1218,26 @@ define <vscale x 1 x i16> @splice_nxv1i16_offset_zero(<vscale x 1 x i16> %a, <vs
}
define <vscale x 1 x i16> @splice_nxv1i16_offset_negone(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
-; CHECK-LABEL: splice_nxv1i16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1i16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1i16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -1)
ret <vscale x 1 x i16> %res
}
@@ -1110,15 +1303,26 @@ define <vscale x 2 x i16> @splice_nxv2i16_offset_zero(<vscale x 2 x i16> %a, <vs
}
define <vscale x 2 x i16> @splice_nxv2i16_offset_negone(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
-; CHECK-LABEL: splice_nxv2i16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv2i16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2i16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -1)
ret <vscale x 2 x i16> %res
}
@@ -1184,15 +1388,26 @@ define <vscale x 4 x i16> @splice_nxv4i16_offset_zero(<vscale x 4 x i16> %a, <vs
}
define <vscale x 4 x i16> @splice_nxv4i16_offset_negone(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
-; CHECK-LABEL: splice_nxv4i16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv4i16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 1
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv4i16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 1
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -1)
ret <vscale x 4 x i16> %res
}
@@ -1513,15 +1728,26 @@ define <vscale x 1 x i32> @splice_nxv1i32_offset_zero(<vscale x 1 x i32> %a, <vs
}
define <vscale x 1 x i32> @splice_nxv1i32_offset_negone(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
-; CHECK-LABEL: splice_nxv1i32_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1i32_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1i32_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -1)
ret <vscale x 1 x i32> %res
}
@@ -1587,15 +1813,26 @@ define <vscale x 2 x i32> @splice_nxv2i32_offset_zero(<vscale x 2 x i32> %a, <vs
}
define <vscale x 2 x i32> @splice_nxv2i32_offset_negone(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
-; CHECK-LABEL: splice_nxv2i32_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv2i32_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2i32_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -1)
ret <vscale x 2 x i32> %res
}
@@ -1912,15 +2149,26 @@ define <vscale x 1 x i64> @splice_nxv1i64_offset_zero(<vscale x 1 x i64> %a, <vs
}
define <vscale x 1 x i64> @splice_nxv1i64_offset_negone(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
-; CHECK-LABEL: splice_nxv1i64_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1i64_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1i64_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -1)
ret <vscale x 1 x i64> %res
}
@@ -2235,15 +2483,26 @@ define <vscale x 1 x bfloat> @splice_nxv1bf16_offset_zero(<vscale x 1 x bfloat>
}
define <vscale x 1 x bfloat> @splice_nxv1bf16_offset_negone(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) #0 {
-; CHECK-LABEL: splice_nxv1bf16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1bf16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1bf16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x bfloat> @llvm.vector.splice.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, i32 -1)
ret <vscale x 1 x bfloat> %res
}
@@ -2309,15 +2568,26 @@ define <vscale x 2 x bfloat> @splice_nxv2bf16_offset_zero(<vscale x 2 x bfloat>
}
define <vscale x 2 x bfloat> @splice_nxv2bf16_offset_negone(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {
-; CHECK-LABEL: splice_nxv2bf16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv2bf16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2bf16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 -1)
ret <vscale x 2 x bfloat> %res
}
@@ -2383,15 +2653,26 @@ define <vscale x 4 x bfloat> @splice_nxv4bf16_offset_zero(<vscale x 4 x bfloat>
}
define <vscale x 4 x bfloat> @splice_nxv4bf16_offset_negone(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {
-; CHECK-LABEL: splice_nxv4bf16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv4bf16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 1
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv4bf16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 1
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 -1)
ret <vscale x 4 x bfloat> %res
}
@@ -2712,15 +2993,26 @@ define <vscale x 1 x half> @splice_nxv1f16_offset_zero(<vscale x 1 x half> %a, <
}
define <vscale x 1 x half> @splice_nxv1f16_offset_negone(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
-; CHECK-LABEL: splice_nxv1f16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1f16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1f16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x half> @llvm.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -1)
ret <vscale x 1 x half> %res
}
@@ -2786,15 +3078,26 @@ define <vscale x 2 x half> @splice_nxv2f16_offset_zero(<vscale x 2 x half> %a, <
}
define <vscale x 2 x half> @splice_nxv2f16_offset_negone(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
-; CHECK-LABEL: splice_nxv2f16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv2f16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2f16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -1)
ret <vscale x 2 x half> %res
}
@@ -2860,15 +3163,26 @@ define <vscale x 4 x half> @splice_nxv4f16_offset_zero(<vscale x 4 x half> %a, <
}
define <vscale x 4 x half> @splice_nxv4f16_offset_negone(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
-; CHECK-LABEL: splice_nxv4f16_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv4f16_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 1
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv4f16_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 1
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -1)
ret <vscale x 4 x half> %res
}
@@ -3189,15 +3503,26 @@ define <vscale x 1 x float> @splice_nxv1f32_offset_zero(<vscale x 1 x float> %a,
}
define <vscale x 1 x float> @splice_nxv1f32_offset_negone(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
-; CHECK-LABEL: splice_nxv1f32_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1f32_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1f32_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x float> @llvm.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -1)
ret <vscale x 1 x float> %res
}
@@ -3263,15 +3588,26 @@ define <vscale x 2 x float> @splice_nxv2f32_offset_zero(<vscale x 2 x float> %a,
}
define <vscale x 2 x float> @splice_nxv2f32_offset_negone(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
-; CHECK-LABEL: splice_nxv2f32_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv2f32_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2f32_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -1)
ret <vscale x 2 x float> %res
}
@@ -3588,15 +3924,26 @@ define <vscale x 1 x double> @splice_nxv1f64_offset_zero(<vscale x 1 x double> %
}
define <vscale x 1 x double> @splice_nxv1f64_offset_negone(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
-; CHECK-LABEL: splice_nxv1f64_offset_negone:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: ret
+; NOVLDEP-LABEL: splice_nxv1f64_offset_negone:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 3
+; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv1f64_offset_negone:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 3
+; VLDEP-NEXT: addi a0, a0, -1
+; VLDEP-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
+; VLDEP-NEXT: ret
%res = call <vscale x 1 x double> @llvm.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -1)
ret <vscale x 1 x double> %res
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 439974d56e389..9b02b0c919a4f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \
-; RUN: -target-abi=lp64d -verify-machineinstrs -O2 < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v -verify-machineinstrs -O2 < %s | FileCheck %s --check-prefixes=CHECK,NODEPVL
+; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v,+vl-dependent-latency -verify-machineinstrs -O2 < %s | FileCheck %s --check-prefixes=CHECK,DEPVL
declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
declare i64 @llvm.riscv.vsetvlimax(i64, i64)
@@ -753,3 +753,113 @@ while.body:
while.end:
ret i64 0
}
+
+define <vscale x 1 x i64> @vslideup_vl1(<vscale x 1 x i64> %a) nounwind {
+; NODEPVL-LABEL: vslideup_vl1:
+; NODEPVL: # %bb.0: # %entry
+; NODEPVL-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; NODEPVL-NEXT: vslideup.vi v9, v8, 1
+; NODEPVL-NEXT: vadd.vv v8, v9, v9
+; NODEPVL-NEXT: ret
+;
+; DEPVL-LABEL: vslideup_vl1:
+; DEPVL: # %bb.0: # %entry
+; DEPVL-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; DEPVL-NEXT: vslideup.vi v9, v8, 1
+; DEPVL-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; DEPVL-NEXT: vadd.vv v8, v9, v9
+; DEPVL-NEXT: ret
+entry:
+ %1 = tail call <vscale x 1 x i64> @llvm.riscv.vslideup(
+ <vscale x 1 x i64> poison,
+ <vscale x 1 x i64> %a,
+ i64 1,
+ i64 1,
+ i64 3)
+ %2 = tail call <vscale x 1 x i64> @llvm.riscv.vadd(
+ <vscale x 1 x i64> poison,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %1,
+ i64 2)
+ ret <vscale x 1 x i64> %2
+}
+
+define <vscale x 1 x i64> @vslidedown_vl1(<vscale x 1 x i64> %a) nounwind {
+; NODEPVL-LABEL: vslidedown_vl1:
+; NODEPVL: # %bb.0: # %entry
+; NODEPVL-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; NODEPVL-NEXT: vslidedown.vi v8, v8, 1
+; NODEPVL-NEXT: vadd.vv v8, v8, v8
+; NODEPVL-NEXT: ret
+;
+; DEPVL-LABEL: vslidedown_vl1:
+; DEPVL: # %bb.0: # %entry
+; DEPVL-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; DEPVL-NEXT: vslidedown.vi v8, v8, 1
+; DEPVL-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; DEPVL-NEXT: vadd.vv v8, v8, v8
+; DEPVL-NEXT: ret
+entry:
+ %1 = tail call <vscale x 1 x i64> @llvm.riscv.vslidedown(
+ <vscale x 1 x i64> poison,
+ <vscale x 1 x i64> %a,
+ i64 1,
+ i64 1,
+ i64 3)
+ %2 = tail call <vscale x 1 x i64> @llvm.riscv.vadd(
+ <vscale x 1 x i64> poison,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %1,
+ i64 2)
+ ret <vscale x 1 x i64> %2
+}
+
+
+define <vscale x 1 x i64> @vmv.v.x_vl1() nounwind {
+; NODEPVL-LABEL: vmv.v.x_vl1:
+; NODEPVL: # %bb.0: # %entry
+; NODEPVL-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; NODEPVL-NEXT: vmv.v.i v8, 1
+; NODEPVL-NEXT: vadd.vv v8, v8, v8
+; NODEPVL-NEXT: ret
+;
+; DEPVL-LABEL: vmv.v.x_vl1:
+; DEPVL: # %bb.0: # %entry
+; DEPVL-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; DEPVL-NEXT: vmv.v.i v8, 1
+; DEPVL-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; DEPVL-NEXT: vadd.vv v8, v8, v8
+; DEPVL-NEXT: ret
+entry:
+ %1 = tail call <vscale x 1 x i64> @llvm.riscv.vmv.v.x(
+ <vscale x 1 x i64> poison,
+ i64 1,
+ i64 1)
+ %2 = tail call <vscale x 1 x i64> @llvm.riscv.vadd(
+ <vscale x 1 x i64> poison,
+ <vscale x 1 x i64> %1,
+ <vscale x 1 x i64> %1,
+ i64 2)
+ ret <vscale x 1 x i64> %2
+}
+
+define <vscale x 1 x double> @vfmv.v.f_vl1(double %f) nounwind {
+; CHECK-LABEL: vfmv.v.f_vl1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: vfadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+entry:
+ %1 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f(
+ <vscale x 1 x double> poison,
+ double %f,
+ i64 1)
+ %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd(
+ <vscale x 1 x double> poison,
+ <vscale x 1 x double> %1,
+ <vscale x 1 x double> %1,
+ i64 7,
+ i64 2)
+ ret <vscale x 1 x double> %2
+}
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