[llvm] [RISCV] Support LLVM IR intrinsics for XAndesVSIntLoad (PR #147493)

[Pengcheng Wang via llvm-commits]

================
@@ -0,0 +1,222 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+xandesvsintload \
+; RUN:   -verify-machineinstrs -target-abi=ilp32 | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvsintload \
+; RUN:   -verify-machineinstrs -target-abi=lp64 | FileCheck %s
+
+define <vscale x 1 x i8> @intrinsic_nds_vln_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_nds_vln_v_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT:    nds.vln8.v v8, (a0)
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8(
+    <vscale x 1 x i8> undef,
----------------
wangpc-pp wrote:

undef -> poison?

https://github.com/llvm/llvm-project/pull/147493