[llvm] [AMDGPU] VOPD/VOPD3 changes for gfx1250 (PR #147602)

[via llvm-commits]

github-actions[bot] wrote:

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp llvm/lib/Target/AMDGPU/GCNSubtarget.h llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp llvm/lib/Target/AMDGPU/GCNVOPDUtils.h llvm/lib/Target/AMDGPU/SIDefines.h llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 41d06b42c..645055183 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -339,9 +339,7 @@ public:
     return isRegOrInline(AMDGPU::VS_64RegClassID, MVT::f64);
   }
 
-  bool isVRegWithInputMods(unsigned RCID) const {
-    return isRegClass(RCID);
-  }
+  bool isVRegWithInputMods(unsigned RCID) const { return isRegClass(RCID); }
 
   bool isVRegWithFP32InputMods() const {
     return isVRegWithInputMods(AMDGPU::VGPR_32RegClassID);
@@ -1788,8 +1786,8 @@ private:
   bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSOPLiteral(const MCInst &Inst) const;
   bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
-  std::optional<unsigned>
-  checkVOPDRegBankConstraints(const MCInst &Inst, bool AsVOPD3);
+  std::optional<unsigned> checkVOPDRegBankConstraints(const MCInst &Inst,
+                                                      bool AsVOPD3);
   bool validateVOPD(const MCInst &Inst, const OperandVector &Operands);
   bool tryVOPD(const MCInst &Inst);
   bool tryVOPD3(const MCInst &Inst);
@@ -3844,8 +3842,8 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(
   return false;
 }
 
-std::optional<unsigned> AMDGPUAsmParser::checkVOPDRegBankConstraints(
-    const MCInst &Inst, bool AsVOPD3) {
+std::optional<unsigned>
+AMDGPUAsmParser::checkVOPDRegBankConstraints(const MCInst &Inst, bool AsVOPD3) {
 
   const unsigned Opcode = Inst.getOpcode();
   if (!isVOPD(Opcode))
@@ -3878,9 +3876,8 @@ std::optional<unsigned> AMDGPUAsmParser::checkVOPDRegBankConstraints(
         return I;
     }
 
-    for (auto OpName : {OpName::vsrc1X, OpName::vsrc1Y,
-                        OpName::vsrc2X, OpName::vsrc2Y,
-                        OpName::imm}) {
+    for (auto OpName : {OpName::vsrc1X, OpName::vsrc1Y, OpName::vsrc2X,
+                        OpName::vsrc2Y, OpName::imm}) {
       int I = getNamedOperandIdx(Opcode, OpName);
       if (I == -1)
         continue;
@@ -3891,15 +3888,14 @@ std::optional<unsigned> AMDGPUAsmParser::checkVOPDRegBankConstraints(
   }
 
   const auto &InstInfo = getVOPDInstInfo(Opcode, &MII);
-  auto InvalidCompOprIdx =
-      InstInfo.getInvalidCompOperandIndex(getVRegIdx, *TRI, SkipSrc,
-                                          AllowSameVGPR, AsVOPD3);
+  auto InvalidCompOprIdx = InstInfo.getInvalidCompOperandIndex(
+      getVRegIdx, *TRI, SkipSrc, AllowSameVGPR, AsVOPD3);
 
   return InvalidCompOprIdx;
 }
 
-bool AMDGPUAsmParser::validateVOPD(
-    const MCInst &Inst, const OperandVector &Operands) {
+bool AMDGPUAsmParser::validateVOPD(const MCInst &Inst,
+                                   const OperandVector &Operands) {
 
   unsigned Opcode = Inst.getOpcode();
   bool AsVOPD3 = MII.get(Opcode).TSFlags & SIInstrFlags::VOPD3;
@@ -9366,8 +9362,8 @@ void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {
       addOp(CInfo.getIndexOfDstInParsedOperands());
   }
 
-  int BitOp3Idx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
-                                             AMDGPU::OpName::bitop3);
+  int BitOp3Idx =
+      AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::bitop3);
   if (BitOp3Idx != -1) {
     OptionalImmIndexMap OptIdx;
     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands.back());
diff --git a/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp b/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
index 26322a4de..27f40f170 100644
--- a/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
@@ -168,7 +168,8 @@ public:
             return false;
           // checkVOPDRegConstraints cares about program order, but doReplace
           // cares about X-Y order in the constituted VOPD
-          return llvm::checkVOPDRegConstraints(*SII, *FirstMI, *SecondMI, VOPD3);
+          return llvm::checkVOPDRegConstraints(*SII, *FirstMI, *SecondMI,
+                                               VOPD3);
         };
 
         if (checkVOPD(false) || (HasVOPD3 && checkVOPD(true))) {
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index ae5db01f6..cee1abf2f 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -36,8 +36,7 @@ using namespace llvm;
 
 bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII,
                                    const MachineInstr &FirstMI,
-                                   const MachineInstr &SecondMI,
-                                   bool IsVOPD3) {
+                                   const MachineInstr &SecondMI, bool IsVOPD3) {
   namespace VOPD = AMDGPU::VOPD;
 
   const MachineFunction *MF = FirstMI.getMF();
@@ -136,9 +135,9 @@ bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII,
 
       // Neg is allowed, other modifiers are not. NB: even though sext has the
       // same value as neg, there are no combinable instructions with sext.
-      for (auto OpName : {AMDGPU::OpName::src0_modifiers,
-                          AMDGPU::OpName::src1_modifiers,
-                          AMDGPU::OpName::src2_modifiers}) {
+      for (auto OpName :
+           {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
+            AMDGPU::OpName::src2_modifiers}) {
         const MachineOperand *Mods = TII.getNamedOperand(MI, OpName);
         if (Mods && (Mods->getImm() & ~SISrcMods::NEG))
           return false;
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.h b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.h
index 4d7f6c0ef..f776ae95e 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.h
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.h
@@ -23,8 +23,7 @@ class SIInstrInfo;
 
 bool checkVOPDRegConstraints(const SIInstrInfo &TII,
                              const MachineInstr &FirstMI,
-                             const MachineInstr &SecondMI,
-                             bool IsVOPD3);
+                             const MachineInstr &SecondMI, bool IsVOPD3);
 
 std::unique_ptr<ScheduleDAGMutation> createVOPDPairingMutation();
 

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https://github.com/llvm/llvm-project/pull/147602