[llvm] [Hexagon]Handle bitcast of i32/v2i16/v4i8 -> v32i1 when Hvx is enabled (PR #147466)

[Shivam Gupta via llvm-commits]

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@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s
+
+define void @bitcast_i32_to_v32i1(ptr %in, ptr %out) {
+; CHECK-LABEL: bitcast_i32_to_v32i1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %entry
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3:2 = combine(#-1,##.LCPI0_0)
+; CHECK-NEXT:     allocframe(r29,#128):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    .cfi_def_cfa r30, 8
+; CHECK-NEXT:    .cfi_offset r31, -4
+; CHECK-NEXT:    .cfi_offset r30, -8
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r29 = and(r29,#-128)
+; CHECK-NEXT:     r0 = memw(r0+#0)
+; CHECK-NEXT:     v1 = vmem(r2+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0 = vsplat(r0)
+; CHECK-NEXT:     r5 = add(r29,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0 = vand(v0,v1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     q0 = vand(v0,r3)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0 = vand(q0,r3)
+; CHECK-NEXT:     vmem(r5+#0) = v0.new
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r4 = memw(r5+#0)
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xgupta wrote:

I asked the auto generated tests as it is in our testing guidelines - https://www.llvm.org/docs/TestingGuide.html#best-practices-for-regression-tests. and recently @RKSimon also regenerating few Hexagon tests's check lines with the script https://github.com/llvm/llvm-project/commits/main/llvm/test/CodeGen/Hexagon. 

https://github.com/llvm/llvm-project/pull/147466