[llvm] [ARM] Port shouldBeAdjustedToZero to ARM (PR #147565)

via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 8 09:52:47 PDT 2025


github-actions[bot] wrote:

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:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/ARM/ARMISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index b1a6d2da0..bfa83fc79 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4841,8 +4841,8 @@ static bool isFloatingPointZero(SDValue Op) {
 
 // TODO: This is copied from AArch64TargetLowering.cpp, which only has
 // ands, subs, and adds affecting flags. In ARM, we have more than that, so this
-// should be expanded to cover all the cases where we can adjust the condition code
-// to zero.
+// should be expanded to cover all the cases where we can adjust the condition
+// code to zero.
 static bool shouldBeAdjustedToZero(SDValue LHS, APInt C, ISD::CondCode &CC) {
   // TODO: Cover all cases where a comparison with 0 would be profitable..
   if (LHS.getOpcode() != ISD::AND)

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https://github.com/llvm/llvm-project/pull/147565


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