[llvm] [ARM] Port shouldBeAdjustedToZero to ARM (PR #147565)

[via llvm-commits]

https://github.com/AZero13 created https://github.com/llvm/llvm-project/pull/147565

None

>From 0ffab4f49d3e495f045b4a907ad5a7c6a2398355 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 8 Jul 2025 12:45:49 -0400
Subject: [PATCH] [ARM] Port shouldBeAdjustedToZero to ARM

---
 llvm/lib/Target/ARM/ARMISelLowering.cpp | 31 +++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 6b85e62d2eb8b..2bee993416297 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4839,14 +4839,41 @@ static bool isFloatingPointZero(SDValue Op) {
   return false;
 }
 
+// TODO: This is copied from AArch64TargetLowering.cpp, which only has
+// ands, subs, and adds affecting flags. In ARM, we have more than that, so this
+// should be expanded to cover all the cases where we can adjust the condition code
+// to zero.
+static bool shouldBeAdjustedToZero(SDValue LHS, APInt C, ISD::CondCode &CC) {
+  // TODO: Cover all cases where a comparison with 0 would be profitable.
+  if (LHS.getOpcode() != ISD::AND && LHS.getOpcode() != AArch64ISD::ANDS)
+    return false;
+
+  if (C.isOne() && (CC == ISD::SETLT || CC == ISD::SETGE)) {
+    CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
+    return true;
+  }
+
+  if (C.isAllOnes() && (CC == ISD::SETLE || CC == ISD::SETGT)) {
+    CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
+    return true;
+  }
+
+  return false;
+}
+
 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
 /// the given operands.
 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                      SDValue &ARMcc, SelectionDAG &DAG,
                                      const SDLoc &dl) const {
   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
-    unsigned C = RHSC->getZExtValue();
-    if (!isLegalICmpImmediate((int32_t)C)) {
+    APInt CInt = RHSC->getAPIntValue();
+    unsigned C = CInt.getZExtValue();
+    if (shouldBeAdjustedToZero(LHS, CInt, CC)) {
+      // Adjust the constant to zero.
+      // CC has already been adjusted.
+      RHS = DAG.getConstant(0, DL, VT);
+    } else if (!isLegalICmpImmediate((int32_t)C)) {
       // Constant does not fit, try adjusting it by one.
       switch (CC) {
       default: break;