[clang] [llvm] [LLVM][AArch64] Relax SVE codegen predicates for sm4 instructions (PR #147524)

[Paul Walker via llvm-commits]

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@@ -370,8 +370,11 @@ def FeatureSVEAES : ExtensionWithMArch<"sve-aes", "SVEAES",
 def FeatureAliasSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
   "", "Shorthand for +sve2+sve-aes", [FeatureSVE2, FeatureSVEAES]>;
 
-def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
-  "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
+def FeatureSVESM4 : ExtensionWithMArch<"sve-sm4", "SVESM4", "FEAT_SVE_SM4",
+  "Enable SM4 SVE instructions", [FeatureSM4]>;
----------------
paulwalker-arm wrote:

```suggestion
  "Enable SVE SM4 instructions", [FeatureSM4]>;
```
to make the text consistent with sve-aes and sve-sha3 documentation.

https://github.com/llvm/llvm-project/pull/147524