[clang] [llvm] [LLVM][AArch64] Relax SVE codegen predicates for sm4 instructions (PR #147524)
Elvina Yakubova via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 8 06:43:02 PDT 2025
https://github.com/ElvinaYakubova created https://github.com/llvm/llvm-project/pull/147524
Adds sve-sm4 to reference FEAT_SVE_SM4 without specifically enabling SVE2.
>From ebeb06ea91035be22d3395f86d8e2cf513a77ccc Mon Sep 17 00:00:00 2001
From: Elvina Yakubova <eyakubova at nvidia.com>
Date: Fri, 4 Jul 2025 07:04:44 -0700
Subject: [PATCH] [LLVM][AArch64] Relax SVE codegen predicates for sm4
instructions
Adds sve-sm4 to reference FEAT_SVE_SM4 without specifically enabling SVE2.
---
clang/test/CodeGen/AArch64/fmv-dependencies.c | 2 +-
clang/test/Driver/aarch64-implied-sve-features.c | 6 +++---
.../print-enabled-extensions/aarch64-fujitsu-monaka.c | 2 +-
.../test/Driver/print-enabled-extensions/aarch64-gb10.c | 2 +-
.../test/Driver/print-enabled-extensions/aarch64-grace.c | 2 +-
.../Driver/print-enabled-extensions/aarch64-olympus.c | 2 +-
clang/test/Driver/print-supported-extensions-aarch64.c | 3 ++-
llvm/lib/Target/AArch64/AArch64.td | 2 +-
llvm/lib/Target/AArch64/AArch64Features.td | 7 +++++--
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 8 ++++----
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 4 ++--
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 3 ++-
llvm/lib/TargetParser/AArch64TargetParser.cpp | 7 +++++++
llvm/test/CodeGen/AArch64/sve2-intrinsics-sm4.ll | 1 +
llvm/test/MC/AArch64/SVE2/directive-arch-negative.s | 2 +-
.../MC/AArch64/SVE2/directive-arch_extension-negative.s | 2 +-
llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s | 2 +-
llvm/test/MC/AArch64/SVE2/sm4e.s | 2 +-
llvm/test/MC/AArch64/SVE2/sm4ekey.s | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 9 +++++++++
21 files changed, 48 insertions(+), 26 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/fmv-dependencies.c b/clang/test/CodeGen/AArch64/fmv-dependencies.c
index a97c4e95cd032..8f7f23f93dfea 100644
--- a/clang/test/CodeGen/AArch64/fmv-dependencies.c
+++ b/clang/test/CodeGen/AArch64/fmv-dependencies.c
@@ -189,6 +189,6 @@ int caller() {
// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-aes,+sve2,+sve2-aes,+v8a"
// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-bitperm,+sve2,+sve2-bitperm,+v8a"
// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve-sha3,+sve2,+sve2-sha3,+v8a"
-// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve2,+sve2-sm4,+v8a"
+// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve-sm4,+sve2,+sve2-sm4,+v8a"
// CHECK: attributes #[[wfxt]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
// CHECK: attributes #[[cssc]] = { {{.*}} "target-features"="+cssc,+fp-armv8,+neon,+outline-atomics,+v8a"
diff --git a/clang/test/Driver/aarch64-implied-sve-features.c b/clang/test/Driver/aarch64-implied-sve-features.c
index 18c39974a5c14..1bda2f529fc70 100644
--- a/clang/test/Driver/aarch64-implied-sve-features.c
+++ b/clang/test/Driver/aarch64-implied-sve-features.c
@@ -49,7 +49,7 @@
// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-sha3" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4-REVERT
-// SVE2-SM4-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sm4"
+// SVE2-SM4-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-sm4" "-target-feature" "+sve2" "-target-feature" "-sve2-sm4"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3
// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve-sha3" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3"
@@ -61,14 +61,14 @@
// SVE2-AES: "-target-feature" "+sve" "-target-feature" "+sve-aes" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4
-// SVE2-SM4: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sm4"
+// SVE2-SM4: "-target-feature" "+sve" "-target-feature" "+sve-sm4" "-target-feature" "+sve2" "-target-feature" "+sve2-sm4"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-bitperm+nosve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SUBFEATURE-MIX
// SVE2-SUBFEATURE-MIX: "-target-feature" "+sve" "-target-feature" "+sve-bitperm" "-target-feature" "+sve2" "-target-feature" "+sve2-bitperm"
// SVE2-SUBFEATURE-NOT: sve2-aes
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SUBFEATURE-CONFLICT
-// SVE2-SUBFEATURE-CONFLICT: "-target-feature" "+sve" "-target-feature" "-sve2" "-target-feature" "-sve2-sm4"
+// SVE2-SUBFEATURE-CONFLICT: "-target-feature" "+sve" "-target-feature" "-sve-sm4" "-target-feature" "-sve2" "-target-feature" "-sve2-sm4"
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT
// SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve2-aes"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c b/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
index 8576edff9bcbe..af543daf1a0e4 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
@@ -71,7 +71,7 @@
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
-// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
+// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-gb10.c b/clang/test/Driver/print-enabled-extensions/aarch64-gb10.c
index 589f7e3e5ee4e..025286e3be479 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-gb10.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-gb10.c
@@ -59,7 +59,7 @@
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
-// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
+// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
index bb24dfbbc0702..95fc02888a8fc 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
@@ -55,7 +55,7 @@
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
-// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
+// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c b/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
index 0cfb9e1fb9817..75bdf8d9aca16 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
@@ -71,7 +71,7 @@
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
-// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
+// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE instructions
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index af4db9944c2df..40613eb1897df 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -93,11 +93,12 @@
// CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
// CHECK-NEXT: sve-sha3 FEAT_SVE_SHA3 Enable SVE SHA3 instructions
+// CHECK-NEXT: sve-sm4 FEAT_SVE_SM4 Enable SM4 SVE instructions
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
// CHECK-NEXT: sve2-aes Shorthand for +sve2+sve-aes
// CHECK-NEXT: sve2-bitperm Shorthand for +sve2+sve-bitperm
// CHECK-NEXT: sve2-sha3 Shorthand for +sve2+sve-sha3
-// CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions
+// CHECK-NEXT: sve2-sm4 Shorthand for +sve2+sve-sm4
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions
// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 25cdcae4e41de..86f95488e6bb7 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -63,7 +63,7 @@ def SVE2p1Unsupported : AArch64Unsupported;
def SVE2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasNonStreamingSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
- HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVE2SM4, HasSVEBitPerm,
+ HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVESM4, HasSVEBitPerm,
HasSVEB16B16],
SVE2p1Unsupported.F);
}
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 05562516e5198..55e3530ea69e9 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -370,8 +370,11 @@ def FeatureSVEAES : ExtensionWithMArch<"sve-aes", "SVEAES",
def FeatureAliasSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
"", "Shorthand for +sve2+sve-aes", [FeatureSVE2, FeatureSVEAES]>;
-def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
- "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
+def FeatureSVESM4 : ExtensionWithMArch<"sve-sm4", "SVESM4", "FEAT_SVE_SM4",
+ "Enable SM4 SVE instructions", [FeatureSM4]>;
+
+def FeatureAliasSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4",
+ "", "Shorthand for +sve2+sve-sm4", [FeatureSVE2, FeatureSVESM4]>;
def FeatureSVESHA3 : ExtensionWithMArch<"sve-sha3", "SVESHA3", "FEAT_SVE_SHA3",
"Enable SVE SHA3 instructions", [FeatureSHA3]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0cb7b02d84a6e..811877ffacedb 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -151,8 +151,8 @@ def HasSVE2p1 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasS
AssemblerPredicateWithAll<(all_of FeatureSVE2p1), "sve2p1">;
def HasSVEAES : Predicate<"Subtarget->hasSVEAES()">,
AssemblerPredicateWithAll<(all_of FeatureSVEAES), "sve-aes">;
-def HasSVE2SM4 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SM4()">,
- AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">;
+def HasSVESM4 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVESM4()">,
+ AssemblerPredicateWithAll<(all_of FeatureSVESM4), "sve-sm4">;
def HasSVESHA3 : Predicate<"Subtarget->hasSVESHA3()">,
AssemblerPredicateWithAll<(all_of FeatureSVESHA3), "sve-sha3">;
def HasSVEBitPerm : Predicate<"Subtarget->hasSVEBitPerm()">,
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 4484951821337..5379305bc7a7f 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -906,7 +906,7 @@ def ProcessorFeatures {
list<SubtargetFeature> MONAKA = [HasV9_3aOps, FeaturePerfMon, FeatureCCIDX,
FeatureFPAC, FeatureFP16FML, FeatureRandGen,
FeatureSSBS, FeatureLS64, FeatureCLRBHB,
- FeatureSPECRES2, FeatureSVEAES, FeatureSVE2SM4,
+ FeatureSPECRES2, FeatureSVEAES, FeatureSVESM4,
FeatureSVESHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE,
FeatureMEC, FeatureFAMINMAX, FeatureFP8DOT2, FeatureFP8DOT4,
FeatureFP8FMA, FeatureLUT];
@@ -921,7 +921,7 @@ def ProcessorFeatures {
FeatureMTE, FeaturePerfMon, FeatureRandGen,
FeatureSPE, FeatureSPE_EEF, FeatureSSBS,
FeatureSVEBitPerm, FeatureSVESHA3,
- FeatureSVE2SM4, FeatureSVEAES];
+ FeatureSVESM4, FeatureSVEAES, FeatureSVE2];
list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON,FeaturePerfMon];
list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
@@ -1117,8 +1117,8 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureSSBS, FeatureCCIDX,
FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> GB10 = !listconcat(X925, [FeatureSVEAES, FeatureSVESHA3, FeatureSVE2SM4]);
- list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVESHA3]);
+ list<SubtargetFeature> GB10 = !listconcat(X925, [FeatureSVEAES, FeatureSVESHA3, FeatureSVESM4]);
+ list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVESM4, FeatureSVEAES, FeatureSVESHA3]);
// ETE and TRBE are future architecture extensions. We temporarily enable them
// by default for users targeting generic AArch64. The extensions do not
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 91a9d21fa7b2c..10f04263902df 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -4109,12 +4109,12 @@ let Predicates = [HasSVEAES, HasNonStreamingSVE_or_SSVE_AES] in {
defm PMULLT_ZZZ_Q : sve2_wide_int_arith_pmul<0b00, 0b11011, "pmullt", int_aarch64_sve_pmullt_pair>;
}
-let Predicates = [HasSVE2SM4] in {
+let Predicates = [HasSVESM4] in {
// SVE2 crypto constructive binary operations
defm SM4EKEY_ZZZ_S : sve2_crypto_cons_bin_op<0b0, "sm4ekey", ZPR32, int_aarch64_sve_sm4ekey, nxv4i32>;
// SVE2 crypto destructive binary operations
def SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32, int_aarch64_sve_sm4e, nxv4i32>;
-} // End HasSVE2SM4
+} // End HasSVESM4
let Predicates = [HasSVESHA3, HasNonStreamingSVE_or_SME2p1] in {
// SVE2 crypto constructive binary operations
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 07c4302cf3d25..1ca61f5c6b349 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3742,7 +3742,8 @@ static const struct Extension {
{"sve2", {AArch64::FeatureSVE2}},
{"sve-aes", {AArch64::FeatureSVEAES}},
{"sve2-aes", {AArch64::FeatureAliasSVE2AES, AArch64::FeatureSVEAES}},
- {"sve2-sm4", {AArch64::FeatureSVE2SM4}},
+ {"sve-sm4", {AArch64::FeatureSVESM4}},
+ {"sve2-sm4", {AArch64::FeatureAliasSVE2SM4, AArch64::FeatureSVESM4}},
{"sve-sha3", {AArch64::FeatureSVESHA3}},
{"sve2-sha3", {AArch64::FeatureAliasSVE2SHA3, AArch64::FeatureSVESHA3}},
{"sve-bitperm", {AArch64::FeatureSVEBitPerm}},
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index c17fa729bac4f..9432fc2c4ac8d 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -298,6 +298,13 @@ void AArch64::ExtensionSet::disable(ArchExtKind E) {
if (E == AEK_SVE2AES)
disable(AEK_SVEAES);
+ // sve2-sm4 was historically associated with both FEAT_SVE2 and
+ // FEAT_SVE_SM4, the latter is now associated with sve-sm4 and sve2-sm4 has
+ // become shorthand for +sve2+sve-sm4. For backwards compatibility, when we
+ // disable sve2-sm4 we must also disable sve-sm4.
+ if (E == AEK_SVE2SM4)
+ disable(AEK_SVESM4);
+
// sve2-sha3 was historically associated with both FEAT_SVE2 and
// FEAT_SVE_SHA3, the latter is now associated with sve-sha3 and sve2-sha3 has
// become shorthand for +sve2+sve-sha3. For backwards compatibility, when we
diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-sm4.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-sm4.ll
index de5af6ce0ae99..fb7dcb3485c68 100644
--- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-sm4.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-sm4.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-sm4 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sve-sm4 < %s | FileCheck %s
;
; SM4E
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
index c3e19a7ad4d03..b20fed789a8ed 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
@@ -20,7 +20,7 @@ aesd z23.b, z23.b, z13.b
.arch armv9-a+sve2-sm4
.arch armv9-a+nosve2-sm4
sm4e z0.s, z0.s, z0.s
-// CHECK: error: instruction requires: sve2-sm4
+// CHECK: error: instruction requires: sve-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.arch armv9-a+sve2-sha3
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index c2ec716e45d5a..73114e57fc18a 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -22,7 +22,7 @@ aesd z23.b, z23.b, z13.b
.arch_extension sve2-sm4
.arch_extension nosve2-sm4
sm4e z0.s, z0.s, z0.s
-// CHECK: error: instruction requires: sve2-sm4
+// CHECK: error: instruction requires: sve-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.arch_extension sve2-sha3
diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
index 956dcb1a82a6a..e5b2a4c2b57aa 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
@@ -20,7 +20,7 @@ aesd z23.b, z23.b, z13.b
.cpu generic+sve2-sm4
.cpu generic+nosve2-sm4
sm4e z0.s, z0.s, z0.s
-// CHECK: error: instruction requires: sve2-sm4
+// CHECK: error: instruction requires: sve-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
.cpu generic+sve2-sha3
diff --git a/llvm/test/MC/AArch64/SVE2/sm4e.s b/llvm/test/MC/AArch64/SVE2/sm4e.s
index 329484bc4b4a5..5c9745cd90a43 100644
--- a/llvm/test/MC/AArch64/SVE2/sm4e.s
+++ b/llvm/test/MC/AArch64/SVE2/sm4e.s
@@ -13,5 +13,5 @@
sm4e z0.s, z0.s, z31.s
// CHECK-INST: sm4e z0.s, z0.s, z31.s
// CHECK-ENCODING: [0xe0,0xe3,0x23,0x45]
-// CHECK-ERROR: instruction requires: sve2-sm4
+// CHECK-ERROR: instruction requires: sve-sm4
// CHECK-UNKNOWN: 4523e3e0 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/sm4ekey.s b/llvm/test/MC/AArch64/SVE2/sm4ekey.s
index c81e39e19167a..1aee0e509c7e6 100644
--- a/llvm/test/MC/AArch64/SVE2/sm4ekey.s
+++ b/llvm/test/MC/AArch64/SVE2/sm4ekey.s
@@ -13,5 +13,5 @@
sm4ekey z0.s, z1.s, z31.s
// CHECK-INST: sm4ekey z0.s, z1.s, z31.s
// CHECK-ENCODING: [0x20,0xf0,0x3f,0x45]
-// CHECK-ERROR: instruction requires: sve2-sm4
+// CHECK-ERROR: instruction requires: sve-sm4
// CHECK-UNKNOWN: 453ff020 <unknown>
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 1d7ad8ac075f4..aeeea0a391ba9 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1442,6 +1442,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SVEAES, AArch64::AEK_SME_MOP4,
AArch64::AEK_SME_TMOP, AArch64::AEK_SVEBITPERM,
AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
+ AArch64::AEK_SVESM4,
};
std::vector<StringRef> Features;
@@ -1479,6 +1480,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sve2"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve-aes"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-aes"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sve-sm4"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sm4"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve-sha3"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sha3"));
@@ -1653,6 +1655,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sve-f16f32mm", "nosve-f16f32mm", "+sve-f16f32mm", "-sve-f16f32mm"},
{"sve2", "nosve2", "+sve2", "-sve2"},
{"sve-aes", "nosve-aes", "+sve-aes", "-sve-aes"},
+ {"sve-sm4", "nosve-sm4", "+sve-sm4", "-sve-sm4"},
{"sve-sha3", "nosve-sha3", "+sve-sha3", "-sve-sha3"},
{"sve2-aes", "nosve2-aes", "+sve2-aes", "-sve2-aes"},
{"sve2-sm4", "nosve2-sm4", "+sve2-sm4", "-sve2-sm4"},
@@ -2162,6 +2165,12 @@ AArch64ExtensionDependenciesBaseArchTestParams
{"sve2"},
{"sve2-aes", "sve-aes"}},
+ // -sve2-sm4 should disable sve-sm4 (only)
+ {AArch64::ARMV9_6A,
+ {"sve2", "sve-sm4", "nosve2-sm4"},
+ {"sve2"},
+ {"sve2-sm4", "sve-sm4"}},
+
// -sve2-sha3 should disable sve-sha3 (only)
{AArch64::ARMV9_6A,
{"sve2", "sve-sha3", "nosve2-sha3"},
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