[llvm] [LV] Extend FindFirstIV to unsigned case (PR #146386)

[Florian Hahn via llvm-commits]

================
@@ -941,6 +941,205 @@ exit:                                             ; preds = %loop
   ret i16 %spec.select.lcssa
 }
 
+; The signed sentinel value for decreasing-IV vectorization is LONG_MAX, and since
+; the IV hits this value with smin vectorization, it needs to be vectorized with a
+; an unsigned sentinel and umin instead.
+define i64 @select_decreasing_induction_icmp_iv_unsigned(ptr %a) {
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fhahn wrote:

I think even with the negative test case, we still miss important coverage. The IV of the added test will have a full range.

More interestingly, it needs a test where it includes the both signed and unsigned sentinel values w/o being the full range.

Something like

```
define i64 @not_vectorized_select_decreasing_induction_icmp_sentinel_value_start(ptr %a, ptr %b, i64 %rdx.start) {
entry:
  br label %loop

loop:
  %iv = phi i64 [ -1, %entry ], [ %iv.next, %loop ]
  %rdx = phi i64 [ %rdx.start, %entry ], [ %cond, %loop ]
  %iv.next = add i64 %iv, -1
  %gep.a.iv = getelementptr inbounds i64, ptr %a, i64 %iv.next
  %ld.a = load i64, ptr %gep.a.iv, align 8
  %gep.b.iv = getelementptr inbounds i64, ptr %b, i64 %iv.next
  %ld.b = load i64, ptr %gep.b.iv, align 8
  %cmp.a.b = icmp sgt i64 %ld.a, %ld.b
  %cond = select i1 %cmp.a.b, i64 %iv.next, i64 %rdx
  %exit.cond = icmp ne i64 %iv.next, 0
  br i1 %exit.cond, label %loop, label %exit

exit:
  ret i64 %cond
}
```

https://github.com/llvm/llvm-project/pull/146386