[llvm] [VPlan] Fix miscompile after PR #142433. (PR #147398)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 8 04:24:26 PDT 2025
================
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-linux-gnu"
+
+define i64 @test(ptr %arg2, i64 %dim) #0 {
+; CHECK-LABEL: define i64 @test(
+; CHECK-SAME: ptr [[ARG2:%.*]], i64 [[DIM:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[START:.*]]:
+; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 1)
+; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP4]], <4 x i1> splat (i1 true), <4 x i1> zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[TMP0]], 0
+; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[TMP1]], 0
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP2]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[TMP3]], 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i64> poison, i64 [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i64> [[TMP10]], i64 [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i64> [[TMP11]], i64 [[TMP8]], i32 2
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i64> [[TMP12]], i64 [[TMP9]], i32 3
+; CHECK-NEXT: [[TMP14:%.*]] = trunc <4 x i64> [[TMP13]] to <4 x i32>
+; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt <4 x i32> zeroinitializer, [[TMP14]]
+; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP15]], <4 x double> splat (double 1.000000e+00), <4 x double> zeroinitializer
+; CHECK-NEXT: [[TMP17:%.*]] = select <4 x i1> [[TMP4]], <4 x i1> zeroinitializer, <4 x i1> zeroinitializer
+; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP5]], [[TMP17]]
+; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP17]], <4 x double> zeroinitializer, <4 x double> [[TMP16]]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[TMP18]], i32 0
+; CHECK-NEXT: br i1 [[TMP19]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
+; CHECK: [[PRED_STORE_IF]]:
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x double> [[PREDPHI]], i32 0
+; CHECK-NEXT: store double [[TMP20]], ptr null, align 8
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
+; CHECK: [[PRED_STORE_CONTINUE]]:
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP18]], i32 1
+; CHECK-NEXT: br i1 [[TMP21]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
+; CHECK: [[PRED_STORE_IF1]]:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x double> [[PREDPHI]], i32 1
+; CHECK-NEXT: store double [[TMP22]], ptr null, align 8
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
+; CHECK: [[PRED_STORE_CONTINUE2]]:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[TMP18]], i32 2
+; CHECK-NEXT: br i1 [[TMP23]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
+; CHECK: [[PRED_STORE_IF3]]:
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x double> [[PREDPHI]], i32 2
+; CHECK-NEXT: store double [[TMP24]], ptr null, align 8
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
+; CHECK: [[PRED_STORE_CONTINUE4]]:
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x i1> [[TMP18]], i32 3
+; CHECK-NEXT: br i1 [[TMP25]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]]
+; CHECK: [[PRED_STORE_IF5]]:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x double> [[PREDPHI]], i32 3
+; CHECK-NEXT: store double [[TMP26]], ptr null, align 8
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
+; CHECK: [[PRED_STORE_CONTINUE6]]:
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
+; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[LOOP_EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, %[[START]] ]
+; CHECK-NEXT: br label %[[LOOP_BODY:.*]]
+; CHECK: [[LOOP_BODY]]:
+; CHECK-NEXT: [[INVAR_021:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INVAR_INC11:%.*]], %[[AFTER:.*]] ]
+; CHECK-NEXT: br i1 false, label %[[AFTER]], label %[[CHECK_TRUE:.*]]
+; CHECK: [[LOOP_EXIT]]:
+; CHECK-NEXT: ret i64 0
+; CHECK: [[AFTER]]:
+; CHECK-NEXT: [[RET_VALUE_ADDR_0:%.*]] = phi double [ [[TMP32:%.*]], %[[CHECK_TRUE]] ], [ 0.000000e+00, %[[LOOP_BODY]] ]
+; CHECK-NEXT: store double [[RET_VALUE_ADDR_0]], ptr null, align 8
+; CHECK-NEXT: [[INVAR_INC11]] = add i64 [[INVAR_021]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INVAR_021]], 1
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[LOOP_EXIT]], label %[[LOOP_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[CHECK_TRUE]]:
+; CHECK-NEXT: [[TMP27:%.*]] = sub nsw i64 [[INVAR_021]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
+; CHECK-NEXT: [[TMP29:%.*]] = icmp sgt i32 0, [[TMP28]]
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr [16 x [16 x double]], ptr [[ARG2]], i64 0, i64 [[DIM]], i64 [[TMP27]]
+; CHECK-NEXT: [[TMP31:%.*]] = load double, ptr [[TMP30]], align 8
+; CHECK-NEXT: [[TMP32]] = select i1 [[TMP29]], double 1.000000e+00, double 0.000000e+00
+; CHECK-NEXT: br label %[[AFTER]]
+;
+start:
+ br label %loop_body
+
+loop_body: ; preds = %after, %start
----------------
fhahn wrote:
```suggestion
loop.header:
```
https://github.com/llvm/llvm-project/pull/147398
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