[llvm] CodeGen: Remove redundant REQUIRES registerd-target from backend tests (PR #147475)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 8 01:02:03 PDT 2025
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/147475
These are already applied to all the tests in the target subdirectory
>From 9d662b3deaf22f6101e4889ef92422d6307a9552 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 8 Jul 2025 16:58:28 +0900
Subject: [PATCH] CodeGen: Remove redundant REQUIRES registerd-target from
backend tests
These are already applied to all the tests in the target subdirectory
---
llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll | 2 +-
llvm/test/CodeGen/AArch64/dump-schedule-trace.mir | 2 +-
llvm/test/CodeGen/AArch64/force-enable-intervals.mir | 6 +++---
.../CodeGen/AArch64/misched-detail-resource-booking-01.mir | 2 +-
.../CodeGen/AArch64/misched-detail-resource-booking-02.mir | 4 ++--
.../test/CodeGen/AArch64/misched-sort-resource-in-trace.mir | 2 +-
.../ARM/misched-prevent-erase-history-of-subunits.mir | 2 +-
llvm/test/CodeGen/SystemZ/systemz-large-stack-frames.ll | 1 -
llvm/test/CodeGen/SystemZ/zos-ppa1.ll | 1 -
llvm/test/CodeGen/WebAssembly/expand-variadic-call.ll | 1 -
llvm/test/CodeGen/WebAssembly/vararg-frame.ll | 1 -
11 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
index 0193952aa2ab2..770035c34812c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG
; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GS
-; REQUIRES: asserts, aarch64-registered-target
+; REQUIRES: asserts
;; add
define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
diff --git a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
index c90d6bd3cb420..ed3169c55e5ca 100644
--- a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
+++ b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
@@ -32,7 +32,7 @@
# RUN: -sched-print-cycles=true -misched-dump-schedule-trace=true \
# RUN: 2>&1 | FileCheck %s --check-prefix=BIDIRECTIONAL
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
---
name: f
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
index 8d47eee1c8e19..a2c1a128687ac 100644
--- a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
+++ b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
@@ -1,12 +1,12 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -misched-dump-reserved-cycles=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
+# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -misched-dump-reserved-cycles=true \
# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
+# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
@@ -18,7 +18,7 @@
# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \
# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s --check-prefix=FORCE
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
---
name: f
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
index 60244d2eb064d..2afc25f895432 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
@@ -14,7 +14,7 @@
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
# RUN: | FileCheck %s
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
--- |
; ModuleID = '../llvm-project/llvm/test/CodeGen/AArch64/aarch64-smull.failing.ll'
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
index de5e6395da73b..c8bb44ca76697 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
@@ -12,7 +12,7 @@
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
# RUN: 2>&1 | FileCheck %s
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
---
name: f
tracksRegLiveness: true
@@ -22,7 +22,7 @@ body: |
$x3 = ADDXrr $x0, $x0
$x4 = ADDXrr $x1, $x1
$x5 = ADDXrr $x2, $x2
-
+
# CHECK-LABEL: Before MISched:
# CHECK-NEXT: # Machine code for function f: IsSSA, NoPHIs, TracksLiveness, NoVRegs
# CHECK-EMPTY:
diff --git a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
index b652d2463fc12..5977870f95f91 100644
--- a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
+++ b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
@@ -18,7 +18,7 @@
# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s
-# REQUIRES: asserts, aarch64-registered-target
+# REQUIRES: asserts
---
name: test
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir b/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
index 7134703851d28..46f3e4b08559a 100644
--- a/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
+++ b/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
@@ -1,7 +1,7 @@
# RUN: llc -mtriple=thumbv7em-unknown-unknown -mcpu=cortex-m7 \
# RUN: -sched-model-force-enable-intervals \
# RUN: %s -run-pass=machine-scheduler -o - 2>&1 -debug | FileCheck %s
-# REQUIRES: arm-registered-target, asserts
+# REQUIRES: asserts
# NOTE: Without the bugfix introduced in this code, the test below
# would raise the assertion "A resource is being overwritten" from
diff --git a/llvm/test/CodeGen/SystemZ/systemz-large-stack-frames.ll b/llvm/test/CodeGen/SystemZ/systemz-large-stack-frames.ll
index 51997a6c17c65..484a9d0c80a13 100644
--- a/llvm/test/CodeGen/SystemZ/systemz-large-stack-frames.ll
+++ b/llvm/test/CodeGen/SystemZ/systemz-large-stack-frames.ll
@@ -1,5 +1,4 @@
; REQUIRES: asserts
-; REQUIRES: systemz-registered-target
; Used to fail with: LLVM ERROR: Error while trying to spill R5D from class ADDR64Bit: Cannot scavenge register without an emergency spill slot!
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
index fc51e9c5eccc5..78593b9f88d1e 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
@@ -1,5 +1,4 @@
; RUN: llc -mtriple s390x-ibm-zos < %s | FileCheck %s
-; REQUIRES: systemz-registered-target
; CHECK: L#EPM_void_test_0: * @void_test
; CHECK: * XPLINK Routine Layout Entry
diff --git a/llvm/test/CodeGen/WebAssembly/expand-variadic-call.ll b/llvm/test/CodeGen/WebAssembly/expand-variadic-call.ll
index 71ad449eeb1ee..a27650f9cd961 100644
--- a/llvm/test/CodeGen/WebAssembly/expand-variadic-call.ll
+++ b/llvm/test/CodeGen/WebAssembly/expand-variadic-call.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --function-signature
; RUN: opt -S --passes=expand-variadics --expand-variadics-override=lowering < %s | FileCheck %s
-; REQUIRES: webassembly-registered-target
target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-n32:64-S128-ni:1:10:20"
target triple = "wasm32-unknown-unknown"
diff --git a/llvm/test/CodeGen/WebAssembly/vararg-frame.ll b/llvm/test/CodeGen/WebAssembly/vararg-frame.ll
index 5c76040325cc9..c8b443c164f32 100644
--- a/llvm/test/CodeGen/WebAssembly/vararg-frame.ll
+++ b/llvm/test/CodeGen/WebAssembly/vararg-frame.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs | FileCheck %s
-; REQUIRES: webassembly-registered-target
target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-n32:64-S128-ni:1:10:20"
target triple = "wasm32-unknown-unknown"
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