[llvm] 9bc3e71 - [ARM][AArch64] Clean up some v3float intrinsic definitions
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 7 23:59:49 PDT 2025
Author: David Green
Date: 2025-07-08T07:59:44+01:00
New Revision: 9bc3e710fbb375723ac1b9e3edb9be34e72926b3
URL: https://github.com/llvm/llvm-project/commit/9bc3e710fbb375723ac1b9e3edb9be34e72926b3
DIFF: https://github.com/llvm/llvm-project/commit/9bc3e710fbb375723ac1b9e3edb9be34e72926b3.diff
LOG: [ARM][AArch64] Clean up some v3float intrinsic definitions
We have had some v3float definitions sneak in and some functions were
incorrectly named after #146691. Use v3f32 instead.
Added:
Modified:
llvm/test/CodeGen/AArch64/extract-vector-elt.ll
llvm/test/CodeGen/AArch64/llvm.frexp.ll
llvm/test/CodeGen/ARM/llvm.frexp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/extract-vector-elt.ll
index 0189f52bbac06..18b028c9898e1 100644
--- a/llvm/test/CodeGen/AArch64/extract-vector-elt.ll
+++ b/llvm/test/CodeGen/AArch64/extract-vector-elt.ll
@@ -331,7 +331,7 @@ define float @extract_v4i32_minimum(<4 x float> %a, <4 x float> %b, i32 %c) {
; CHECK-GI-NEXT: add sp, sp, #16
; CHECK-GI-NEXT: ret
entry:
- %vector = call <4 x float> @llvm.minimum.v4float(<4 x float> %a, <4 x float> %b)
+ %vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
%d = extractelement <4 x float> %vector, i32 %c
ret float %d
}
@@ -367,7 +367,7 @@ define float @extract_v4i32_minimum_build_vector(<4 x float> %a, <4 x float> %b,
; CHECK-GI-NEXT: add sp, sp, #16
; CHECK-GI-NEXT: ret
entry:
- %vector = call <4 x float> @llvm.minimum.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
+ %vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
%d = extractelement <4 x float> %vector, i32 %c
ret float %d
}
@@ -381,7 +381,7 @@ define float @extract_v4i32_minimum_build_vector_const(<4 x float> %a, <4 x floa
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: ret
entry:
- %vector = call <4 x float> @llvm.minimum.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
+ %vector = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
%d = extractelement <4 x float> %vector, i32 1
ret float %d
}
@@ -414,7 +414,7 @@ define float @extract_v4i32_copysign_build_vector(<4 x float> %a, <4 x float> %b
; CHECK-GI-NEXT: add sp, sp, #16
; CHECK-GI-NEXT: ret
entry:
- %vector = call <4 x float> @llvm.copysign.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
+ %vector = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
%d = extractelement <4 x float> %vector, i32 %c
ret float %d
}
@@ -433,7 +433,7 @@ define float @extract_v4i32_copysign_build_vector_const(<4 x float> %a, <4 x flo
; CHECK-GI-NEXT: mov s0, v0.s[2]
; CHECK-GI-NEXT: ret
entry:
- %vector = call <4 x float> @llvm.copysign.v4float(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
+ %vector = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 42.0, float 11.0, float 17.0, float 6.0>)
%d = extractelement <4 x float> %vector, i32 2
ret float %d
}
@@ -508,8 +508,8 @@ entry:
ret i32 %d
}
-define i32 @extract_v4float_fcmp(<4 x float> %a, <4 x float> %b, i32 %c) {
-; CHECK-SD-LABEL: extract_v4float_fcmp:
+define i32 @extract_v4f32_fcmp(<4 x float> %a, <4 x float> %b, i32 %c) {
+; CHECK-SD-LABEL: extract_v4f32_fcmp:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
@@ -524,7 +524,7 @@ define i32 @extract_v4float_fcmp(<4 x float> %a, <4 x float> %b, i32 %c) {
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
;
-; CHECK-GI-LABEL: extract_v4float_fcmp:
+; CHECK-GI-LABEL: extract_v4f32_fcmp:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sub sp, sp, #16
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
@@ -548,8 +548,8 @@ entry:
ret i32 %d
}
-define i32 @extract_v4float_fcmp_const(<4 x float> %a, <4 x float> %b, i32 %c) {
-; CHECK-SD-LABEL: extract_v4float_fcmp_const:
+define i32 @extract_v4f32_fcmp_const(<4 x float> %a, <4 x float> %b, i32 %c) {
+; CHECK-SD-LABEL: extract_v4f32_fcmp_const:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: movi v1.4s, #1
; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v0.4s
@@ -557,7 +557,7 @@ define i32 @extract_v4float_fcmp_const(<4 x float> %a, <4 x float> %b, i32 %c) {
; CHECK-SD-NEXT: mov w0, v0.s[1]
; CHECK-SD-NEXT: ret
;
-; CHECK-GI-LABEL: extract_v4float_fcmp_const:
+; CHECK-GI-LABEL: extract_v4f32_fcmp_const:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: fmov v1.4s, #1.00000000
; CHECK-GI-NEXT: fcmge v2.4s, v0.4s, v1.4s
@@ -680,9 +680,9 @@ define i32 @extract_v4i32_abs(<4 x float> %a, i32 %c) {
; CHECK-GI-NEXT: add sp, sp, #16
; CHECK-GI-NEXT: ret
entry:
- %ceil = call <4 x float> @llvm.ceil.v4float(<4 x float> %a)
- %floor = call <4 x float> @llvm.floor.v4float(<4 x float> %ceil)
- %fabs = call <4 x float> @llvm.fabs.v4float(<4 x float> %floor)
+ %ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)
+ %floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)
+ %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)
%abs = fptosi <4 x float> %fabs to <4 x i32>
%vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)
%d = extractelement <4 x i32> %vector, i32 %c
@@ -708,9 +708,9 @@ define i32 @extract_v4i32_abs_const(<4 x float> %a, i32 %c) {
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
entry:
- %ceil = call <4 x float> @llvm.ceil.v4float(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
- %floor = call <4 x float> @llvm.floor.v4float(<4 x float> %ceil)
- %fabs = call <4 x float> @llvm.fabs.v4float(<4 x float> %floor)
+ %ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
+ %floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)
+ %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)
%abs = fptosi <4 x float> %fabs to <4 x i32>
%vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)
%d = extractelement <4 x i32> %vector, i32 1
@@ -751,9 +751,9 @@ define i32 @extract_v4i32_abs_half_const(<4 x float> %a, i32 %c) {
; CHECK-GI-NEXT: add sp, sp, #16
; CHECK-GI-NEXT: ret
entry:
- %ceil = call <4 x float> @llvm.ceil.v4float(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
- %floor = call <4 x float> @llvm.floor.v4float(<4 x float> %ceil)
- %fabs = call <4 x float> @llvm.fabs.v4float(<4 x float> %floor)
+ %ceil = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float 1.0, float 4.0, float 3.0, float 2.0>)
+ %floor = call <4 x float> @llvm.floor.v4f32(<4 x float> %ceil)
+ %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %floor)
%abs = fptosi <4 x float> %fabs to <4 x i32>
%vector = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %abs, i1 0)
%d = extractelement <4 x i32> %vector, i32 %c
diff --git a/llvm/test/CodeGen/AArch64/llvm.frexp.ll b/llvm/test/CodeGen/AArch64/llvm.frexp.ll
index 092fe16cbc2f3..51400b96e8b77 100644
--- a/llvm/test/CodeGen/AArch64/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AArch64/llvm.frexp.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-gnu-linux < %s | FileCheck -check-prefixes=CHECK %s
; RUN: llc -mtriple=aarch64-windows-pc-msvc < %s | FileCheck -check-prefixes=WINDOWS %s
+
define { half, i32 } @test_frexp_f16_i32(half %a) {
; CHECK-LABEL: test_frexp_f16_i32:
; CHECK: // %bb.0:
@@ -391,8 +392,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
ret <2 x i32> %result.1
}
-define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
-; CHECK-LABEL: test_frexp_v3f16_v3i32:
+define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) {
+; CHECK-LABEL: test_frexp_v3f32_v3i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #80
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
@@ -433,8 +434,8 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
; CHECK-NEXT: add sp, sp, #80
; CHECK-NEXT: ret
;
-; WINDOWS-LABEL: test_frexp_v3f16_v3i32:
-; WINDOWS: .seh_proc test_frexp_v3f16_v3i32
+; WINDOWS-LABEL: test_frexp_v3f32_v3i32:
+; WINDOWS: .seh_proc test_frexp_v3f32_v3i32
; WINDOWS-NEXT: // %bb.0:
; WINDOWS-NEXT: sub sp, sp, #80
; WINDOWS-NEXT: .seh_stackalloc 80
@@ -493,7 +494,7 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
; WINDOWS-NEXT: ret
; WINDOWS-NEXT: .seh_endfunclet
; WINDOWS-NEXT: .seh_endproc
- %result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3float.v3i32(<3 x float> %a)
+ %result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3f32.v3i32(<3 x float> %a)
ret { <3 x float>, <3 x i32> } %result
}
diff --git a/llvm/test/CodeGen/ARM/llvm.frexp.ll b/llvm/test/CodeGen/ARM/llvm.frexp.ll
index 6f21834ea5e39..43edb17fe1081 100644
--- a/llvm/test/CodeGen/ARM/llvm.frexp.ll
+++ b/llvm/test/CodeGen/ARM/llvm.frexp.ll
@@ -141,8 +141,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
ret <2 x i32> %result.1
}
-define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
-; CHECK-LABEL: test_frexp_v3f16_v3i32:
+define { <3 x float>, <3 x i32> } @test_frexp_v3f32_v3i32(<3 x float> %a) {
+; CHECK-LABEL: test_frexp_v3f32_v3i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: vpush {d8, d9}
@@ -174,7 +174,7 @@ define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
- %result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3float.v3i32(<3 x float> %a)
+ %result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3f32.v3i32(<3 x float> %a)
ret { <3 x float>, <3 x i32> } %result
}
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