[llvm] [AArch64] Lower disjoint_or+not to eon. (PR #147279)

Ricardo Jesus via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 7 07:11:14 PDT 2025


================
@@ -30,3 +30,24 @@ entry:
   %shl2 = shl i64 %xor, %xor1
   ret i64 %shl2
 }
+
+; Check that eon is generated if the xor is a disjoint or.
+define i64 @disjoint_or(i64 %a, i64 %b) {
+; CHECK-LABEL: disjoint_or:
+; CHECK: eon
+; CHECK: ret
+  %or = or disjoint i64 %a, %b
----------------
rj-jesus wrote:

No worries at all! I think in this case the disjoint flag should be present in both scalar and vector operations. The difference is that we have dedicated vector patterns that match the whole BSL operation, and they accept any OR node, with or without disjoint. We don't have similar patterns for scalar BSL because we don't have dedicated instructions for them in the base ISA, which means we are dependent on the lowering of the individual operations (such as the EON in this patch).

In any case, if you agree, I'll create a separate PR for vector types NOT (XOR (a, b)) -> BSL2N(a, a, b) such that:
```
  mov     z2.d, #-1
  eor3    z0.d, z0.d, z1.d, z2.d
```
becomes:
```
  bsl2n   z0.d, z0.d, z0.d, z1.d
```

https://github.com/llvm/llvm-project/pull/147279


More information about the llvm-commits mailing list