[llvm] [AArch64] Lower disjoint_or+not to eon. (PR #147279)

[David Sherwood via llvm-commits]

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@@ -30,3 +30,24 @@ entry:
   %shl2 = shl i64 %xor, %xor1
   ret i64 %shl2
 }
+
+; Check that eon is generated if the xor is a disjoint or.
+define i64 @disjoint_or(i64 %a, i64 %b) {
+; CHECK-LABEL: disjoint_or:
+; CHECK: eon
+; CHECK: ret
+  %or = or disjoint i64 %a, %b
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david-arm wrote:

Should this also work for vectors? Is there any value adding a vector variant do you think?

https://github.com/llvm/llvm-project/pull/147279