[llvm] [DAG] SDPatternMatch m_Zero/m_One/m_AllOnes have inconsistent undef h… (PR #147044)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 7 04:25:51 PDT 2025
================
@@ -57925,22 +57925,20 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
}
}
+ SDValue X, Y;
+
// add(psadbw(X,0),psadbw(Y,0)) -> psadbw(add(X,Y),0)
// iff X and Y won't overflow.
- if (Op0.getOpcode() == X86ISD::PSADBW && Op1.getOpcode() == X86ISD::PSADBW &&
- ISD::isBuildVectorAllZeros(Op0.getOperand(1).getNode()) &&
- ISD::isBuildVectorAllZeros(Op1.getOperand(1).getNode())) {
- if (DAG.willNotOverflowAdd(false, Op0.getOperand(0), Op1.getOperand(0))) {
- MVT OpVT = Op0.getOperand(1).getSimpleValueType();
- SDValue Sum =
- DAG.getNode(ISD::ADD, DL, OpVT, Op0.getOperand(0), Op1.getOperand(0));
- return DAG.getNode(X86ISD::PSADBW, DL, VT, Sum,
- getZeroVector(OpVT, Subtarget, DAG, DL));
- }
+ if (sd_match(Op0, m_c_BinOp(X86ISD::PSADBW, m_Value(X), m_Zero())) &&
+ sd_match(Op1, m_c_BinOp(X86ISD::PSADBW, m_Value(Y), m_Zero())) &&
+ DAG.willNotOverflowAdd(/*IsSigned=*/false, X, Y)) {
+ MVT OpVT = X.getSimpleValueType();
+ SDValue Sum = DAG.getNode(ISD::ADD, DL, OpVT, X, Y);
+ return DAG.getNode(X86ISD::PSADBW, DL, VT, Sum,
+ getZeroVector(OpVT, Subtarget, DAG, DL));
----------------
woruyu wrote:
Done!
https://github.com/llvm/llvm-project/pull/147044
More information about the llvm-commits
mailing list