[llvm] [LoongArch] Optimize 128-to-256-bit vector insertion and 256-to-128-bit subvector extraction (PR #146300)
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Mon Jul 7 00:51:27 PDT 2025
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@@ -1879,6 +1873,35 @@ def : Pat<(loongarch_xvmskgez (v32i8 LASX256:$vj)), (PseudoXVMSKGEZ_B LASX256:$v
def : Pat<(loongarch_xvmskeqz (v32i8 LASX256:$vj)), (PseudoXVMSKEQZ_B LASX256:$vj)>;
def : Pat<(loongarch_xvmsknez (v32i8 LASX256:$vj)), (PseudoXVMSKNEZ_B LASX256:$vj)>;
+// Subvector tricks
+// Patterns for insert_subvector/extract_subvector
+multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT,
+ RegisterClass RC, ValueType VT,
+ int hiIdx, SubRegIndex subIdx> {
+ // A 128-bit subvector extract from the first 256-bit vector position is a
+ // subregister copy that needs no instruction. Likewise, a 128-bit subvector
+ // insert to the first 256-bit vector position is a subregister copy that needs
+ // no instruction.
+ def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
+ (subVT (EXTRACT_SUBREG RC:$src, subIdx))>;
+ def : Pat<(VT (insert_subvector undef_or_freeze_undef, subRC:$src, (iPTR 0))),
+ (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>;
+
+ def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR hiIdx))),
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heiher wrote:
If the output operand and an input operand are assigned the same physical register, does that mean the input operand's live range has ended?
https://github.com/llvm/llvm-project/pull/146300
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