[llvm] aec8883 - MC: Remove unneeded MCFixupKind casts
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 5 14:43:39 PDT 2025
Author: Fangrui Song
Date: 2025-07-05T14:43:34-07:00
New Revision: aec88832df5e8c1dcbe259a6cb3d82d44b89ff23
URL: https://github.com/llvm/llvm-project/commit/aec88832df5e8c1dcbe259a6cb3d82d44b89ff23
DIFF: https://github.com/llvm/llvm-project/commit/aec88832df5e8c1dcbe259a6cb3d82d44b89ff23.diff
LOG: MC: Remove unneeded MCFixupKind casts
Added:
Modified:
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index 838ac748c4580..6e5a69030dbc6 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -303,7 +303,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
const MCExpr *Expr = MO.getExpr();
// Encode the 12 bits of the fixup.
- MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
+ MCFixupKind Kind = AArch64::fixup_aarch64_add_imm12;
addFixup(Fixups, 0, Expr, Kind);
++MCNumFixups;
@@ -413,8 +413,8 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
return MO.getImm();
assert(MO.isExpr() && "Unexpected movz/movk immediate");
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- MCFixupKind(AArch64::fixup_aarch64_movw)));
+ Fixups.push_back(
+ MCFixup::create(0, MO.getExpr(), AArch64::fixup_aarch64_movw));
++MCNumFixups;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index fa8bd267e5823..c56b589519533 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -987,7 +987,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
"Thumb mode requires
diff erent encoding");
Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
isAdd = false; // 'U' bit is set as part of the fixup.
- MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
+ MCFixupKind Kind = ARM::fixup_arm_ldst_abs_12;
addFixup(Fixups, 0, MO1.getExpr(), Kind);
}
} else if (MO.isExpr()) {
@@ -995,9 +995,9 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
isAdd = false; // 'U' bit is set as part of the fixup.
MCFixupKind Kind;
if (isThumb2(STI))
- Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
+ Kind = ARM::fixup_t2_ldst_pcrel_12;
else
- Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
+ Kind = ARM::fixup_arm_ldst_pcrel_12;
addFixup(Fixups, 0, MO.getExpr(), Kind);
++MCNumCPRelocations;
@@ -1122,7 +1122,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
- MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
+ MCFixupKind Kind = ARM::fixup_t2_pcrel_10;
addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
@@ -1241,22 +1241,22 @@ uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
case ARM::S_HI_8_15:
if (!isThumb(STI))
llvm_unreachable(":upper_8_15: not supported in Arm state");
- Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_8_15);
+ Kind = ARM::fixup_arm_thumb_upper_8_15;
break;
case ARM::S_HI_0_7:
if (!isThumb(STI))
llvm_unreachable(":upper_0_7: not supported in Arm state");
- Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_0_7);
+ Kind = ARM::fixup_arm_thumb_upper_0_7;
break;
case ARM::S_LO_8_15:
if (!isThumb(STI))
llvm_unreachable(":lower_8_15: not supported in Arm state");
- Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_8_15);
+ Kind = ARM::fixup_arm_thumb_lower_8_15;
break;
case ARM::S_LO_0_7:
if (!isThumb(STI))
llvm_unreachable(":lower_0_7: not supported in Arm state");
- Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_0_7);
+ Kind = ARM::fixup_arm_thumb_lower_0_7;
break;
}
@@ -1381,7 +1381,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
- MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
+ MCFixupKind Kind = ARM::fixup_arm_pcrel_10_unscaled;
addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
@@ -1461,9 +1461,9 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind;
if (isThumb2(STI))
- Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
+ Kind = ARM::fixup_t2_pcrel_10;
else
- Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
+ Kind = ARM::fixup_arm_pcrel_10;
addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
@@ -1501,9 +1501,9 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind;
if (isThumb2(STI))
- Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
+ Kind = ARM::fixup_t2_pcrel_9;
else
- Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
+ Kind = ARM::fixup_arm_pcrel_9;
addFixup(Fixups, 0, Expr, Kind);
++MCNumCPRelocations;
@@ -1529,7 +1529,7 @@ unsigned ARMMCCodeEmitter::getModImmOpValue(const MCInst &MI, unsigned Op,
if (MO.isExpr()) {
const MCExpr *Expr = MO.getExpr();
// Fixups resolve to plain values that need to be encoded.
- MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
+ MCFixupKind Kind = ARM::fixup_arm_mod_imm;
addFixup(Fixups, 0, Expr, Kind);
return 0;
}
@@ -1547,7 +1547,7 @@ unsigned ARMMCCodeEmitter::getT2SOImmOpValue(const MCInst &MI, unsigned Op,
if (MO.isExpr()) {
const MCExpr *Expr = MO.getExpr();
// Fixups resolve to plain values that need to be encoded.
- MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
+ MCFixupKind Kind = ARM::fixup_t2_so_imm;
addFixup(Fixups, 0, Expr, Kind);
return 0;
}
@@ -1995,7 +1995,7 @@ ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
assert(BranchMO.isExpr());
const MCExpr *DiffExpr = MCBinaryExpr::createSub(
MO.getExpr(), BranchMO.getExpr(), CTX);
- MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
+ MCFixupKind Kind = ARM::fixup_bfcsel_else_target;
addFixup(Fixups, 0, DiffExpr, Kind);
return 0;
}
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
index d2397aca0a82d..4bb16e237db48 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
@@ -166,7 +166,7 @@ unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
OffsetBits = OffsetOp.getImm();
} else if (OffsetOp.isExpr()) {
OffsetBits = 0;
- addFixup(Fixups, 0, OffsetOp.getExpr(), MCFixupKind(AVR::fixup_6));
+ addFixup(Fixups, 0, OffsetOp.getExpr(), AVR::fixup_6);
} else {
llvm_unreachable("Invalid value for offset");
}
@@ -215,7 +215,7 @@ unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
auto MO = MI.getOperand(OpNo);
if (MO.isExpr()) {
- MCFixupKind FixupKind = static_cast<MCFixupKind>(AVR::fixup_call);
+ MCFixupKind FixupKind = AVR::fixup_call;
addFixup(Fixups, 0, MO.getExpr(), FixupKind);
return 0;
}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
index 95a4d39970234..5f9f55eb606c2 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
@@ -176,7 +176,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
const MCOperand &MO = MI.getOperand(Idx);
assert(MO.isExpr() && "Unexpected MO type.");
- MCFixupKind Kind = MCFixupKind(CSKY::fixup_csky_pcrel_imm26_scale2);
+ MCFixupKind Kind = CSKY::fixup_csky_pcrel_imm26_scale2;
if (MO.getExpr()->getKind() == MCExpr::Specifier)
Kind = getTargetFixup(MO.getExpr());
@@ -190,7 +190,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
const MCOperand &MO = MI.getOperand(Idx);
assert(MO.isExpr() && "Unexpected MO type.");
- MCFixupKind Kind = MCFixupKind(CSKY::fixup_csky_pcrel_imm18_scale2);
+ MCFixupKind Kind = CSKY::fixup_csky_pcrel_imm18_scale2;
if (MO.getExpr()->getKind() == MCExpr::Specifier)
Kind = getTargetFixup(MO.getExpr());
@@ -481,23 +481,23 @@ MCFixupKind CSKYMCCodeEmitter::getTargetFixup(const MCExpr *Expr) const {
default:
llvm_unreachable("Unhandled fixup kind!");
case CSKY::S_ADDR:
- return MCFixupKind(CSKY::fixup_csky_addr32);
+ return CSKY::fixup_csky_addr32;
case CSKY::S_ADDR_HI16:
- return MCFixupKind(CSKY::fixup_csky_addr_hi16);
+ return CSKY::fixup_csky_addr_hi16;
case CSKY::S_ADDR_LO16:
- return MCFixupKind(CSKY::fixup_csky_addr_lo16);
+ return CSKY::fixup_csky_addr_lo16;
case CSKY::S_GOT:
- return MCFixupKind(CSKY::fixup_csky_got32);
+ return CSKY::fixup_csky_got32;
case CSKY::S_GOTPC:
- return MCFixupKind(CSKY::fixup_csky_gotpc);
+ return CSKY::fixup_csky_gotpc;
case CSKY::S_GOTOFF:
- return MCFixupKind(CSKY::fixup_csky_gotoff);
+ return CSKY::fixup_csky_gotoff;
case CSKY::S_PLT:
- return MCFixupKind(CSKY::fixup_csky_plt32);
+ return CSKY::fixup_csky_plt32;
case CSKY::S_PLT_IMM18_BY4:
- return MCFixupKind(CSKY::fixup_csky_plt_imm18_scale4);
+ return CSKY::fixup_csky_plt_imm18_scale4;
case CSKY::S_GOT_IMM18_BY4:
- return MCFixupKind(CSKY::fixup_csky_got_imm18_scale4);
+ return CSKY::fixup_csky_got_imm18_scale4;
}
}
diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
index d1b2da40446a6..84dc4b8312370 100644
--- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
@@ -290,8 +290,7 @@ unsigned LanaiMCCodeEmitter::getBranchTargetOpValue(
if (MCOp.isReg() || MCOp.isImm())
return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
- Fixups.push_back(MCFixup::create(
- 0, MCOp.getExpr(), static_cast<MCFixupKind>(Lanai::FIXUP_LANAI_25)));
+ Fixups.push_back(MCFixup::create(0, MCOp.getExpr(), Lanai::FIXUP_LANAI_25));
return 0;
}
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
index 51c7deead0528..1b8893029bb33 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
@@ -265,23 +265,17 @@ getRelocPairForSize(unsigned Size) {
default:
llvm_unreachable("unsupported fixup size");
case 6:
- return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD6),
- MCFixupKind(ELF::R_LARCH_SUB6));
+ return std::make_pair(ELF::R_LARCH_ADD6, ELF::R_LARCH_SUB6);
case 8:
- return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD8),
- MCFixupKind(ELF::R_LARCH_SUB8));
+ return std::make_pair(ELF::R_LARCH_ADD8, ELF::R_LARCH_SUB8);
case 16:
- return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD16),
- MCFixupKind(ELF::R_LARCH_SUB16));
+ return std::make_pair(ELF::R_LARCH_ADD16, ELF::R_LARCH_SUB16);
case 32:
- return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD32),
- MCFixupKind(ELF::R_LARCH_SUB32));
+ return std::make_pair(ELF::R_LARCH_ADD32, ELF::R_LARCH_SUB32);
case 64:
- return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD64),
- MCFixupKind(ELF::R_LARCH_SUB64));
+ return std::make_pair(ELF::R_LARCH_ADD64, ELF::R_LARCH_SUB64);
case 128:
- return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD_ULEB128),
- MCFixupKind(ELF::R_LARCH_SUB_ULEB128));
+ return std::make_pair(ELF::R_LARCH_ADD_ULEB128, ELF::R_LARCH_SUB_ULEB128);
}
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
index 17f56d572d3b0..c2169beea2753 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -357,41 +357,38 @@ std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
return StringSwitch<std::optional<MCFixupKind>>(Name)
.Case("R_MIPS_NONE", FK_NONE)
.Case("R_MIPS_32", FK_Data_4)
- .Case("R_MIPS_CALL_HI16", (MCFixupKind)Mips::fixup_Mips_CALL_HI16)
- .Case("R_MIPS_CALL_LO16", (MCFixupKind)Mips::fixup_Mips_CALL_LO16)
- .Case("R_MIPS_CALL16", (MCFixupKind)Mips::fixup_Mips_CALL16)
- .Case("R_MIPS_GOT16", (MCFixupKind)Mips::fixup_Mips_GOT)
- .Case("R_MIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_Mips_GOT_PAGE)
- .Case("R_MIPS_GOT_OFST", (MCFixupKind)Mips::fixup_Mips_GOT_OFST)
- .Case("R_MIPS_GOT_DISP", (MCFixupKind)Mips::fixup_Mips_GOT_DISP)
- .Case("R_MIPS_GOT_HI16", (MCFixupKind)Mips::fixup_Mips_GOT_HI16)
- .Case("R_MIPS_GOT_LO16", (MCFixupKind)Mips::fixup_Mips_GOT_LO16)
- .Case("R_MIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_Mips_GOTTPREL)
- .Case("R_MIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_Mips_DTPREL_HI)
- .Case("R_MIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_Mips_DTPREL_LO)
- .Case("R_MIPS_TLS_GD", (MCFixupKind)Mips::fixup_Mips_TLSGD)
- .Case("R_MIPS_TLS_LDM", (MCFixupKind)Mips::fixup_Mips_TLSLDM)
- .Case("R_MIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_Mips_TPREL_HI)
- .Case("R_MIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_Mips_TPREL_LO)
- .Case("R_MICROMIPS_CALL16", (MCFixupKind)Mips::fixup_MICROMIPS_CALL16)
- .Case("R_MICROMIPS_GOT_DISP", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_DISP)
- .Case("R_MICROMIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_PAGE)
- .Case("R_MICROMIPS_GOT_OFST", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_OFST)
- .Case("R_MICROMIPS_GOT16", (MCFixupKind)Mips::fixup_MICROMIPS_GOT16)
- .Case("R_MICROMIPS_TLS_GOTTPREL",
- (MCFixupKind)Mips::fixup_MICROMIPS_GOTTPREL)
+ .Case("R_MIPS_CALL_HI16", Mips::fixup_Mips_CALL_HI16)
+ .Case("R_MIPS_CALL_LO16", Mips::fixup_Mips_CALL_LO16)
+ .Case("R_MIPS_CALL16", Mips::fixup_Mips_CALL16)
+ .Case("R_MIPS_GOT16", Mips::fixup_Mips_GOT)
+ .Case("R_MIPS_GOT_PAGE", Mips::fixup_Mips_GOT_PAGE)
+ .Case("R_MIPS_GOT_OFST", Mips::fixup_Mips_GOT_OFST)
+ .Case("R_MIPS_GOT_DISP", Mips::fixup_Mips_GOT_DISP)
+ .Case("R_MIPS_GOT_HI16", Mips::fixup_Mips_GOT_HI16)
+ .Case("R_MIPS_GOT_LO16", Mips::fixup_Mips_GOT_LO16)
+ .Case("R_MIPS_TLS_GOTTPREL", Mips::fixup_Mips_GOTTPREL)
+ .Case("R_MIPS_TLS_DTPREL_HI16", Mips::fixup_Mips_DTPREL_HI)
+ .Case("R_MIPS_TLS_DTPREL_LO16", Mips::fixup_Mips_DTPREL_LO)
+ .Case("R_MIPS_TLS_GD", Mips::fixup_Mips_TLSGD)
+ .Case("R_MIPS_TLS_LDM", Mips::fixup_Mips_TLSLDM)
+ .Case("R_MIPS_TLS_TPREL_HI16", Mips::fixup_Mips_TPREL_HI)
+ .Case("R_MIPS_TLS_TPREL_LO16", Mips::fixup_Mips_TPREL_LO)
+ .Case("R_MICROMIPS_CALL16", Mips::fixup_MICROMIPS_CALL16)
+ .Case("R_MICROMIPS_GOT_DISP", Mips::fixup_MICROMIPS_GOT_DISP)
+ .Case("R_MICROMIPS_GOT_PAGE", Mips::fixup_MICROMIPS_GOT_PAGE)
+ .Case("R_MICROMIPS_GOT_OFST", Mips::fixup_MICROMIPS_GOT_OFST)
+ .Case("R_MICROMIPS_GOT16", Mips::fixup_MICROMIPS_GOT16)
+ .Case("R_MICROMIPS_TLS_GOTTPREL", Mips::fixup_MICROMIPS_GOTTPREL)
.Case("R_MICROMIPS_TLS_DTPREL_HI16",
- (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_HI16)
+ Mips::fixup_MICROMIPS_TLS_DTPREL_HI16)
.Case("R_MICROMIPS_TLS_DTPREL_LO16",
- (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
- .Case("R_MICROMIPS_TLS_GD", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD)
- .Case("R_MICROMIPS_TLS_LDM", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM)
- .Case("R_MICROMIPS_TLS_TPREL_HI16",
- (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
- .Case("R_MICROMIPS_TLS_TPREL_LO16",
- (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
- .Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR)
- .Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR)
+ Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
+ .Case("R_MICROMIPS_TLS_GD", Mips::fixup_MICROMIPS_TLS_GD)
+ .Case("R_MICROMIPS_TLS_LDM", Mips::fixup_MICROMIPS_TLS_LDM)
+ .Case("R_MICROMIPS_TLS_TPREL_HI16", Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
+ .Case("R_MICROMIPS_TLS_TPREL_LO16", Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
+ .Case("R_MIPS_JALR", Mips::fixup_Mips_JALR)
+ .Case("R_MICROMIPS_JALR", Mips::fixup_MICROMIPS_JALR)
.Default(MCAsmBackend::getFixupKind(Name));
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 2f2c3584d23c7..a8369f2b28fb7 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -744,7 +744,7 @@ unsigned MipsMCCodeEmitter::getImmOpValue(const MCInst &MI, const MCOperand &MO,
return Res;
unsigned MIFrm = MipsII::getFormat(MCII.get(MI.getOpcode()).TSFlags);
if (!isa<MCSpecifierExpr>(Expr) && MIFrm == MipsII::FrmI) {
- addFixup(Fixups, 0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16));
+ addFixup(Fixups, 0, Expr, Mips::fixup_Mips_AnyImm16);
return 0;
}
return getExprOpValue(Expr, Fixups, STI);
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index 02269f6a56676..c69fc68ab5af1 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -1035,42 +1035,42 @@ MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
void MipsTargetELFStreamer::emitGPRel32Value(const MCExpr *Value) {
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
- MCFixupKind(Mips::fixup_Mips_GPREL32)));
+ Mips::fixup_Mips_GPREL32));
DF->appendContents(4, 0);
}
void MipsTargetELFStreamer::emitGPRel64Value(const MCExpr *Value) {
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
- MCFixupKind(Mips::fixup_Mips_GPREL32)));
+ Mips::fixup_Mips_GPREL32));
DF->appendContents(8, 0);
}
void MipsTargetELFStreamer::emitDTPRel32Value(const MCExpr *Value) {
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
- MCFixupKind(Mips::fixup_Mips_DTPREL32)));
+ Mips::fixup_Mips_DTPREL32));
DF->appendContents(4, 0);
}
void MipsTargetELFStreamer::emitDTPRel64Value(const MCExpr *Value) {
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
- MCFixupKind(Mips::fixup_Mips_DTPREL64)));
+ Mips::fixup_Mips_DTPREL64));
DF->appendContents(8, 0);
}
void MipsTargetELFStreamer::emitTPRel32Value(const MCExpr *Value) {
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
- MCFixupKind(Mips::fixup_Mips_TPREL32)));
+ Mips::fixup_Mips_TPREL32));
DF->appendContents(4, 0);
}
void MipsTargetELFStreamer::emitTPRel64Value(const MCExpr *Value) {
MCDataFragment *DF = getStreamer().getOrCreateDataFragment();
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
- MCFixupKind(Mips::fixup_Mips_TPREL64)));
+ Mips::fixup_Mips_TPREL64));
DF->appendContents(8, 0);
}
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index e022da42e36b7..00bb2471c0d2d 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -288,7 +288,7 @@ ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
std::optional<MCFixupKind>
XCOFFPPCAsmBackend::getFixupKind(StringRef Name) const {
return StringSwitch<std::optional<MCFixupKind>>(Name)
- .Case("R_REF", (MCFixupKind)PPC::fixup_ppc_nofixup)
+ .Case("R_REF", PPC::fixup_ppc_nofixup)
.Default(std::nullopt);
}
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index af8628f442cc7..8ed7c68f54e7f 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -236,16 +236,14 @@ uint64_t
PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- return getImm34Encoding(MI, OpNo, Fixups, STI,
- (MCFixupKind)PPC::fixup_ppc_imm34);
+ return getImm34Encoding(MI, OpNo, Fixups, STI, PPC::fixup_ppc_imm34);
}
uint64_t
PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- return getImm34Encoding(MI, OpNo, Fixups, STI,
- (MCFixupKind)PPC::fixup_ppc_pcrel34);
+ return getImm34Encoding(MI, OpNo, Fixups, STI, PPC::fixup_ppc_pcrel34);
}
unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
index b5c23772e6d8c..c1cdf511fae5b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
@@ -71,21 +71,17 @@ getRelocPairForSize(unsigned Size) {
default:
llvm_unreachable("unsupported fixup size");
case 1:
- return std::make_pair(
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD8),
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB8));
+ return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD8,
+ FirstLiteralRelocationKind + ELF::R_RISCV_SUB8);
case 2:
- return std::make_pair(
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD16),
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB16));
+ return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD16,
+ FirstLiteralRelocationKind + ELF::R_RISCV_SUB16);
case 4:
- return std::make_pair(
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD32),
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB32));
+ return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD32,
+ FirstLiteralRelocationKind + ELF::R_RISCV_SUB32);
case 8:
- return std::make_pair(
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD64),
- MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB64));
+ return std::make_pair(FirstLiteralRelocationKind + ELF::R_RISCV_ADD64,
+ FirstLiteralRelocationKind + ELF::R_RISCV_SUB64);
}
}
diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
index 1097bf7cbb4f8..cbaf10fc18b88 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
@@ -156,10 +156,10 @@ void WebAssemblyMCCodeEmitter::encodeInstruction(
const MCOperandInfo &Info = Desc.operands()[I];
switch (Info.OperandType) {
case WebAssembly::OPERAND_I32IMM:
- FixupKind = MCFixupKind(WebAssembly::fixup_sleb128_i32);
+ FixupKind = WebAssembly::fixup_sleb128_i32;
break;
case WebAssembly::OPERAND_I64IMM:
- FixupKind = MCFixupKind(WebAssembly::fixup_sleb128_i64);
+ FixupKind = WebAssembly::fixup_sleb128_i64;
PaddedSize = 10;
break;
case WebAssembly::OPERAND_FUNCTION32:
@@ -169,10 +169,10 @@ void WebAssemblyMCCodeEmitter::encodeInstruction(
case WebAssembly::OPERAND_TYPEINDEX:
case WebAssembly::OPERAND_GLOBAL:
case WebAssembly::OPERAND_TAG:
- FixupKind = MCFixupKind(WebAssembly::fixup_uleb128_i32);
+ FixupKind = WebAssembly::fixup_uleb128_i32;
break;
case WebAssembly::OPERAND_OFFSET64:
- FixupKind = MCFixupKind(WebAssembly::fixup_uleb128_i64);
+ FixupKind = WebAssembly::fixup_uleb128_i64;
PaddedSize = 10;
break;
default:
@@ -181,7 +181,7 @@ void WebAssemblyMCCodeEmitter::encodeInstruction(
} else {
// Variadic expr operands are try_table's catch/catch_ref clauses' tags.
assert(Opcode == WebAssembly::TRY_TABLE_S);
- FixupKind = MCFixupKind(WebAssembly::fixup_uleb128_i32);
+ FixupKind = WebAssembly::fixup_uleb128_i32;
}
Fixups.push_back(
MCFixup::create(OS.tell() - Start, MO.getExpr(), FixupKind));
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
index 065f6850bf99a..3323b387368d6 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
@@ -272,9 +272,8 @@ unsigned X86ELFObjectWriter::getRelocType32(SMLoc Loc, X86::Specifier Specifier,
if (!getContext().getTargetOptions()->X86RelaxRelocations)
return ELF::R_386_GOT32;
- return Kind == MCFixupKind(X86::reloc_signed_4byte_relax)
- ? ELF::R_386_GOT32X
- : ELF::R_386_GOT32;
+ return Kind == X86::reloc_signed_4byte_relax ? ELF::R_386_GOT32X
+ : ELF::R_386_GOT32;
case X86::S_GOTOFF:
assert(!IsPCRel);
if (Type != RT32_32)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 1303dc5fc5da2..5db00a7f17bc2 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -446,7 +446,7 @@ static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
default:
llvm_unreachable("Unsupported signed fixup size!");
case 4:
- return MCFixupKind(X86::reloc_signed_4byte);
+ return X86::reloc_signed_4byte;
}
}
switch (Size) {
@@ -890,8 +890,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB, Fixups,
ImmOffset);
else if (ForceDisp32)
- emitImmediate(Disp, MI.getLoc(), MCFixupKind(X86::reloc_signed_4byte),
- false, StartByte, CB, Fixups);
+ emitImmediate(Disp, MI.getLoc(), X86::reloc_signed_4byte, false, StartByte,
+ CB, Fixups);
}
/// Emit all instruction prefixes.
@@ -1626,8 +1626,8 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
break;
const MCOperand &Op = MI.getOperand(CurOp++);
- emitImmediate(Op, MI.getLoc(), MCFixupKind(X86::reloc_branch_4byte_pcrel),
- true, StartByte, CB, Fixups);
+ emitImmediate(Op, MI.getLoc(), X86::reloc_branch_4byte_pcrel, true,
+ StartByte, CB, Fixups);
break;
}
case X86II::RawFrmMemOffs:
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