[llvm] [ARM] Limit (SELECT_CC setgt, iN lhs, -1, 1, -1) transform to MVT::i32 (PR #147159)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-arm

Author: AZero13 (AZero13)

<details>
<summary>Changes</summary>

Unlike AArch64, here it seems types can be not MVT::i32 

---
Full diff: https://github.com/llvm/llvm-project/pull/147159.diff


1 Files Affected:

- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2d73725291d11..f556647ae1f20 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5527,7 +5527,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
   ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
   ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
   ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
-  if (Op.getValueType().isInteger()) {
+  if (LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
     // Check for sign pattern (SELECT_CC setgt, iN lhs, -1, 1, -1) and transform
     // into (OR (ASR lhs, N-1), 1), which requires less instructions for the
     // supported types.

``````````

</details>


https://github.com/llvm/llvm-project/pull/147159