[llvm] [ARM] Limit (SELECT_CC setgt, iN lhs, -1, 1, -1) transform to MVT::i32 (PR #147159)

[via llvm-commits]

https://github.com/AZero13 created https://github.com/llvm/llvm-project/pull/147159

Unlike AArch64, here it seems types can be not MVT::i32 

>From 00a3feaa839da949d3cbdc8d75e869f50ddc250b Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sat, 5 Jul 2025 14:32:42 -0400
Subject: [PATCH] [ARM] Limit (SELECT_CC setgt, iN lhs, -1, 1, -1) transform to
 MVT::i32

---
 llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2d73725291d11..f556647ae1f20 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5527,7 +5527,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
   ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
   ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
   ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
-  if (Op.getValueType().isInteger()) {
+  if (LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
     // Check for sign pattern (SELECT_CC setgt, iN lhs, -1, 1, -1) and transform
     // into (OR (ASR lhs, N-1), 1), which requires less instructions for the
     // supported types.