[llvm] c203791 - X86: Replace deprecated FK_PCRel_ with FK_Data_ fixup and PCRel flag
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 22:25:07 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T22:25:02-07:00
New Revision: c20379198c7fb66b9514d21ae1e07b0705e3e6fa
URL: https://github.com/llvm/llvm-project/commit/c20379198c7fb66b9514d21ae1e07b0705e3e6fa
DIFF: https://github.com/llvm/llvm-project/commit/c20379198c7fb66b9514d21ae1e07b0705e3e6fa.diff
LOG: X86: Replace deprecated FK_PCRel_ with FK_Data_ fixup and PCRel flag
We will unify the generic fixup kinds FK_Data_ and FK_PCRel_. A
FK_PCRel_ kind is essentially the corresponding FK_Data_ fixup with the
PCRel flag set.
Added:
Modified:
llvm/lib/MC/MCAsmStreamer.cpp
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
llvm/test/MC/ELF/mc-dump.s
Removed:
################################################################################
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 9c6474ccb6174..ccd1fd88c7192 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -2414,9 +2414,14 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
auto Kind = F.getKind();
if (mc::isRelocation(Kind))
OS << ", relocation type: " << Kind;
- else
- OS << ", kind: "
- << getAssembler().getBackend().getFixupKindInfo(Kind).Name;
+ else {
+ OS << ", kind: ";
+ auto Info = getAssembler().getBackend().getFixupKindInfo(Kind);
+ if (F.isPCRel() && StringRef(Info.Name).starts_with("FK_Data_"))
+ OS << "FK_PCRel_" << (Info.TargetSize / 8);
+ else
+ OS << Info.Name;
+ }
OS << '\n';
}
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index eedc81b8dfd7a..d9f398cc2fe25 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -657,15 +657,12 @@ static unsigned getFixupKindSize(unsigned Kind) {
llvm_unreachable("invalid fixup kind!");
case FK_NONE:
return 0;
- case FK_PCRel_1:
case FK_SecRel_1:
case FK_Data_1:
return 1;
- case FK_PCRel_2:
case FK_SecRel_2:
case FK_Data_2:
return 2;
- case FK_PCRel_4:
case X86::reloc_riprel_4byte:
case X86::reloc_riprel_4byte_relax:
case X86::reloc_riprel_4byte_relax_rex:
@@ -680,7 +677,6 @@ static unsigned getFixupKindSize(unsigned Kind) {
case FK_SecRel_4:
case FK_Data_4:
return 4;
- case FK_PCRel_8:
case FK_SecRel_8:
case FK_Data_8:
return 8;
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
index ca2de814bb815..065f6850bf99a 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
@@ -76,7 +76,6 @@ static X86_64RelType getType64(MCFixupKind Kind, X86::Specifier &Specifier,
IsPCRel = true;
return RT64_32;
case FK_Data_4:
- case FK_PCRel_4:
case X86::reloc_riprel_4byte:
case X86::reloc_riprel_4byte_relax:
case X86::reloc_riprel_4byte_relax_rex:
@@ -88,10 +87,8 @@ static X86_64RelType getType64(MCFixupKind Kind, X86::Specifier &Specifier,
case X86::reloc_branch_4byte_pcrel:
Specifier = X86::S_PLT;
return RT64_32;
- case FK_PCRel_2:
case FK_Data_2:
return RT64_16;
- case FK_PCRel_1:
case FK_Data_1:
return RT64_8;
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 1666518e3365c..1303dc5fc5da2 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -358,8 +358,8 @@ class X86MCCodeEmitter : public MCCodeEmitter {
unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
- void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
- unsigned FixupKind, uint64_t StartByte,
+ void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned FixupKind,
+ bool IsPCRel, uint64_t StartByte,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
@@ -441,8 +441,6 @@ static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
/// instruction with the specified TSFlags.
static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
unsigned Size = X86II::getSizeOfImm(TSFlags);
- bool isPCRel = X86II::isImmPCRel(TSFlags);
-
if (X86II::isImmSigned(TSFlags)) {
switch (Size) {
default:
@@ -455,13 +453,13 @@ static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
default:
llvm_unreachable("Invalid generic fixup size!");
case 1:
- return isPCRel ? FK_PCRel_1 : FK_Data_1;
+ return FK_Data_1;
case 2:
- return isPCRel ? FK_PCRel_2 : FK_Data_2;
+ return FK_Data_2;
case 4:
- return isPCRel ? FK_PCRel_4 : FK_Data_4;
+ return FK_Data_4;
case 8:
- return isPCRel ? FK_PCRel_8 : FK_Data_8;
+ return FK_Data_8;
}
}
@@ -506,7 +504,8 @@ static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
const MCInstrDesc &Desc = MCII.get(Opcode);
if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
Opcode != X86::JCC_4) ||
- getImmFixupKind(Desc.TSFlags) != FK_PCRel_4)
+ !(getImmFixupKind(Desc.TSFlags) == FK_Data_4 &&
+ X86II::isImmPCRel(Desc.TSFlags)))
return false;
unsigned CurOp = X86II::getOperandBias(Desc);
@@ -528,17 +527,29 @@ unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
}
void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
- unsigned Size, unsigned FixupKind,
+ unsigned FixupKind, bool PCRel,
uint64_t StartByte,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
int ImmOffset) const {
+ unsigned Size = 4;
+ switch (FixupKind) {
+ case FK_Data_1:
+ Size = 1;
+ break;
+ case FK_Data_2:
+ Size = 2;
+ break;
+ case FK_Data_8:
+ Size = 8;
+ break;
+ }
const MCExpr *Expr = nullptr;
if (DispOp.isImm()) {
// If this is a simple integer displacement that doesn't require a
// relocation, emit it now.
- if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 &&
- FixupKind != FK_PCRel_4) {
+ if (!(is_contained({FK_Data_1, FK_Data_2, FK_Data_4}, FixupKind) &&
+ PCRel)) {
emitConstant(DispOp.getImm() + ImmOffset, Size, CB);
return;
}
@@ -578,33 +589,13 @@ void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
// If the fixup is pc-relative, we need to bias the value to be relative to
// the start of the field, not the end of the field.
- bool PCRel = false;
- switch (FixupKind) {
- case FK_PCRel_1:
- PCRel = true;
- ImmOffset -= 1;
- break;
- case FK_PCRel_2:
- PCRel = true;
- ImmOffset -= 2;
- break;
- case FK_PCRel_4:
- case X86::reloc_riprel_4byte:
- case X86::reloc_riprel_4byte_movq_load:
- case X86::reloc_riprel_4byte_movq_load_rex2:
- case X86::reloc_riprel_4byte_relax:
- case X86::reloc_riprel_4byte_relax_rex:
- case X86::reloc_riprel_4byte_relax_rex2:
- case X86::reloc_branch_4byte_pcrel:
- case X86::reloc_riprel_4byte_relax_evex:
- PCRel = true;
- ImmOffset -= 4;
+ if (PCRel) {
+ ImmOffset -= Size;
// If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
// leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
// this needs to be a GOTPC32 relocation.
- if (startsWithGlobalOffsetTable(Expr) != GOT_None)
+ if (Size == 4 && startsWithGlobalOffsetTable(Expr) != GOT_None)
FixupKind = X86::reloc_global_offset_table;
- break;
}
if (ImmOffset)
@@ -712,8 +703,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
? X86II::getSizeOfImm(TSFlags)
: 0;
- emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
- Fixups, -ImmSize);
+ emitImmediate(Disp, MI.getLoc(), FixupKind, true, StartByte, CB, Fixups,
+ -ImmSize);
return;
}
@@ -767,7 +758,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
}
// Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
emitByte(modRMByte(1, RegOpcodeField, RMfield), CB);
- emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups);
+ emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,
+ Fixups);
return;
}
// This is the [REG]+disp16 case.
@@ -779,7 +771,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
}
// Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
- emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, StartByte, CB, Fixups);
+ emitImmediate(Disp, MI.getLoc(), FK_Data_2, false, StartByte, CB, Fixups);
return;
}
@@ -797,7 +789,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
STI.hasFeature(X86::Is64Bit))) {
if (!BaseReg) { // [disp32] in X86-32 mode
emitByte(modRMByte(0, RegOpcodeField, 5), CB);
- emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, StartByte, CB, Fixups);
+ emitImmediate(Disp, MI.getLoc(), FK_Data_4, false, StartByte, CB, Fixups);
return;
}
@@ -833,8 +825,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
int ImmOffset = 0;
if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);
- emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
- ImmOffset);
+ emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,
+ Fixups, ImmOffset);
return;
}
}
@@ -846,8 +838,8 @@ void X86MCCodeEmitter::emitMemModRMByte(
unsigned Opcode = MI.getOpcode();
unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
: X86::reloc_signed_4byte;
- emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
- Fixups);
+ emitImmediate(Disp, MI.getLoc(), MCFixupKind(FixupKind), false, StartByte,
+ CB, Fixups);
return;
}
@@ -895,11 +887,11 @@ void X86MCCodeEmitter::emitMemModRMByte(
// Do we need to output a displacement?
if (ForceDisp8)
- emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
+ emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB, Fixups,
ImmOffset);
else if (ForceDisp32)
- emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
- StartByte, CB, Fixups);
+ emitImmediate(Disp, MI.getLoc(), MCFixupKind(X86::reloc_signed_4byte),
+ false, StartByte, CB, Fixups);
}
/// Emit all instruction prefixes.
@@ -1634,33 +1626,29 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
break;
const MCOperand &Op = MI.getOperand(CurOp++);
- emitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
- MCFixupKind(X86::reloc_branch_4byte_pcrel), StartByte, CB,
- Fixups);
+ emitImmediate(Op, MI.getLoc(), MCFixupKind(X86::reloc_branch_4byte_pcrel),
+ true, StartByte, CB, Fixups);
break;
}
case X86II::RawFrmMemOffs:
emitByte(BaseOpcode, CB);
- emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
- X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
- StartByte, CB, Fixups);
+ emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
+ X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
++CurOp; // skip segment operand
break;
case X86II::RawFrmImm8:
emitByte(BaseOpcode, CB);
- emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
- X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
+ emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
+ X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
+ emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_1, false,
StartByte, CB, Fixups);
- emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, StartByte,
- CB, Fixups);
break;
case X86II::RawFrmImm16:
emitByte(BaseOpcode, CB);
- emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
- X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
+ emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),
+ X86II::isImmPCRel(TSFlags), StartByte, CB, Fixups);
+ emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_2, false,
StartByte, CB, Fixups);
- emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, StartByte,
- CB, Fixups);
break;
case X86II::AddRegFrm:
@@ -2013,7 +2001,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
assert(Val < 16 && "Immediate operand value out of range");
I8RegNum |= Val;
}
- emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
+ emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), FK_Data_1, false,
StartByte, CB, Fixups);
} else {
// If there is a remaining operand, it must be a trailing immediate. Emit it
@@ -2024,7 +2012,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
unsigned RemaningOps = NumOps - CurOp - 2 * HasTwoConditionalOps;
while (RemaningOps) {
emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
- X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
+ getImmFixupKind(TSFlags), X86II::isImmPCRel(TSFlags),
StartByte, CB, Fixups);
--RemaningOps;
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
index 6bb643b7ace3f..c34425f6661b4 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
@@ -78,11 +78,8 @@ static unsigned getFixupKindLog2Size(unsigned Kind) {
switch (Kind) {
default:
llvm_unreachable("invalid fixup kind!");
- case FK_PCRel_1:
case FK_Data_1: return 0;
- case FK_PCRel_2:
case FK_Data_2: return 1;
- case FK_PCRel_4:
// FIXME: Remove these!!!
case X86::reloc_riprel_4byte:
case X86::reloc_riprel_4byte_relax:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
index 1e2937626d47e..0bfc0e071a66d 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
@@ -45,14 +45,17 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
const MCAsmBackend &MAB) const {
const bool Is64Bit = getMachine() == COFF::IMAGE_FILE_MACHINE_AMD64;
unsigned FixupKind = Fixup.getKind();
+ bool PCRel = Fixup.isPCRel();
if (IsCrossSection) {
// IMAGE_REL_AMD64_REL64 does not exist. We treat FK_Data_8 as FK_PCRel_4 so
// that .quad a-b can lower to IMAGE_REL_AMD64_REL32. This allows generic
// instrumentation to not bother with the COFF limitation. A negative value
// needs attention.
- if (FixupKind == FK_Data_4 || FixupKind == llvm::X86::reloc_signed_4byte ||
- (FixupKind == FK_Data_8 && Is64Bit)) {
- FixupKind = FK_PCRel_4;
+ if (!PCRel &&
+ (FixupKind == FK_Data_4 || FixupKind == llvm::X86::reloc_signed_4byte ||
+ (FixupKind == FK_Data_8 && Is64Bit))) {
+ FixupKind = FK_Data_4;
+ PCRel = true;
} else {
Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
return COFF::IMAGE_REL_AMD64_ADDR32;
@@ -62,7 +65,6 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
auto Spec = Target.getSpecifier();
if (Is64Bit) {
switch (FixupKind) {
- case FK_PCRel_4:
case X86::reloc_riprel_4byte:
case X86::reloc_riprel_4byte_movq_load:
case X86::reloc_riprel_4byte_movq_load_rex2:
@@ -73,6 +75,9 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
case X86::reloc_branch_4byte_pcrel:
return COFF::IMAGE_REL_AMD64_REL32;
case FK_Data_4:
+ if (PCRel)
+ return COFF::IMAGE_REL_AMD64_REL32;
+ [[fallthrough]];
case X86::reloc_signed_4byte:
case X86::reloc_signed_4byte_relax:
if (Spec == MCSymbolRefExpr::VK_COFF_IMGREL32)
@@ -92,11 +97,13 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
}
} else if (getMachine() == COFF::IMAGE_FILE_MACHINE_I386) {
switch (FixupKind) {
- case FK_PCRel_4:
case X86::reloc_riprel_4byte:
case X86::reloc_riprel_4byte_movq_load:
return COFF::IMAGE_REL_I386_REL32;
case FK_Data_4:
+ if (PCRel)
+ return COFF::IMAGE_REL_I386_REL32;
+ [[fallthrough]];
case X86::reloc_signed_4byte:
case X86::reloc_signed_4byte_relax:
if (Spec == MCSymbolRefExpr::VK_COFF_IMGREL32)
diff --git a/llvm/test/MC/ELF/mc-dump.s b/llvm/test/MC/ELF/mc-dump.s
index 2286a0d2510c0..42f91456584a0 100644
--- a/llvm/test/MC/ELF/mc-dump.s
+++ b/llvm/test/MC/ELF/mc-dump.s
@@ -13,7 +13,7 @@
# CHECK-NEXT: Symbol @0 _start
# CHECK-NEXT:0 Org Offset:3 Value:0
# CHECK-NEXT:3 Relaxable Size:2 <MCInst #1996 <MCOperand Expr:.Ltmp0>>
-# CHECK-NEXT: Fixup @1 Value:.Ltmp0-1 Kind:4006
+# CHECK-NEXT: Fixup @1 Value:.Ltmp0-1 Kind:4001
# CHECK-NEXT:5 Data Size:16 [48,8b,04,25,00,00,00,00,48,8b,04,25,00,00,00,00]
# CHECK-NEXT: Fixup @4 Value:f0@<variant 11> Kind:4021
# CHECK-NEXT: Fixup @12 Value:_start@<variant 11> Kind:4021
More information about the llvm-commits
mailing list