[llvm] 7b7dc15 - AVRMCCodeEmitter: Set PCRel at fixup creation
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 18:08:50 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T18:08:46-07:00
New Revision: 7b7dc151a75b80560a034d8cf010efaf8e1edc38
URL: https://github.com/llvm/llvm-project/commit/7b7dc151a75b80560a034d8cf010efaf8e1edc38
DIFF: https://github.com/llvm/llvm-project/commit/7b7dc151a75b80560a034d8cf010efaf8e1edc38.diff
LOG: AVRMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.
Added:
Modified:
llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
index 418bf181a5451..b46376006c810 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
@@ -434,8 +434,8 @@ MCFixupKindInfo AVRAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
// name offset bits flags
{"fixup_32", 0, 32, 0},
- {"fixup_7_pcrel", 3, 7, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_13_pcrel", 0, 12, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_7_pcrel", 3, 7, 0},
+ {"fixup_13_pcrel", 0, 12, 0},
{"fixup_16", 0, 16, 0},
{"fixup_16_pm", 0, 16, 0},
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
index d1a09fb5b2bec..d2397aca0a82d 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
@@ -35,6 +35,17 @@
namespace llvm {
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+ const MCExpr *Value, uint16_t Kind) {
+ bool PCRel = false;
+ switch (Kind) {
+ case AVR::fixup_7_pcrel:
+ case AVR::fixup_13_pcrel:
+ PCRel = true;
+ }
+ Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
/// Performs a post-encoding step on a `LD` or `ST` instruction.
///
/// The encoding of the LD/ST family of instructions is inconsistent w.r.t
@@ -110,7 +121,7 @@ AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isExpr()) {
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(Fixup)));
+ addFixup(Fixups, 0, MO.getExpr(), MCFixupKind(Fixup));
return 0;
}
@@ -155,8 +166,7 @@ unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
OffsetBits = OffsetOp.getImm();
} else if (OffsetOp.isExpr()) {
OffsetBits = 0;
- Fixups.push_back(
- MCFixup::create(0, OffsetOp.getExpr(), MCFixupKind(AVR::fixup_6)));
+ addFixup(Fixups, 0, OffsetOp.getExpr(), MCFixupKind(AVR::fixup_6));
} else {
llvm_unreachable("Invalid value for offset");
}
@@ -190,7 +200,7 @@ unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
}
MCFixupKind FixupKind = static_cast<MCFixupKind>(Fixup);
- Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), FixupKind));
+ addFixup(Fixups, Offset, MO.getExpr(), FixupKind);
return 0;
}
@@ -206,7 +216,7 @@ unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
if (MO.isExpr()) {
MCFixupKind FixupKind = static_cast<MCFixupKind>(AVR::fixup_call);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind));
+ addFixup(Fixups, 0, MO.getExpr(), FixupKind);
return 0;
}
@@ -236,7 +246,7 @@ unsigned AVRMCCodeEmitter::getExprOpValue(const MCExpr *Expr,
}
MCFixupKind FixupKind = static_cast<MCFixupKind>(AVRExpr->getFixupKind());
- Fixups.push_back(MCFixup::create(0, AVRExpr, FixupKind));
+ addFixup(Fixups, 0, AVRExpr, FixupKind);
return 0;
}
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